Add a generic register script handler
This is based on the RCBA configuration setup from haswell. It handles PCI, BARs, IO, MMIO, and baytrail-specific IOSF. I did not extend it to handle MSR yet but that would be another potential register type. There are a number of approaches to this kind of thing, but in the end they have a lot of switch statements and a mass of #defines. I'm not particularly set on any of the details so comments welcome. BUG=chrome-os-partner:23635 BRANCH=rambi TEST=emerge-rambi chromeos-coreboot-rambi Change-Id: Ib873936ecf20fc996a8feeb72b9d04ddb523211f Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175206 Commit-Queue: Aaron Durbin <adurbin@chromium.org> Tested-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4923 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This commit is contained in:
Duncan Laurie
Aaron Durbin
parent
0567c91b22
commit
7274800ea3
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@ -1087,3 +1087,10 @@ config POWER_BUTTON_IS_OPTIONAL
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default n if !(POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE)
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help
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Internal option that controls ENABLE_POWER_BUTTON visibility.
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config REG_SCRIPT
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bool
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default y if ARCH_X86
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default n
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help
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Internal option that controls whether we compile in register scripts.
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@ -0,0 +1,316 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2013 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef REG_SCRIPT_H
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#define REG_SCRIPT_H
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#include <stdint.h>
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#include <arch/io.h>
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#include <device/device.h>
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#include <device/resource.h>
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/*
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* The reg script library is a way to provide data-driven I/O accesses for
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* initializing devices. It currently supports PCI, legacy I/O,
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* memory-mapped I/O, and IOSF accesses.
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*
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* In order to simplify things for the developer the following features
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* are employed:
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* - Chaining of tables that allow runtime tables to chain to compile-time
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* tables.
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* - Notion of current device (device_t) being worked on. This allows for
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* PCI config, io, and mmio on a particular device's resources.
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*
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* Note that when using REG_SCRIPT_COMMAND_NEXT there is an implicit push
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* and pop of the context. A chained reg_script inherits the previous
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* context (such as current device), but it does not impact the previous
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* context in any way.
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*/
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enum {
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REG_SCRIPT_COMMAND_READ,
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REG_SCRIPT_COMMAND_WRITE,
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REG_SCRIPT_COMMAND_RMW,
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REG_SCRIPT_COMMAND_POLL,
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REG_SCRIPT_COMMAND_SET_DEV,
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REG_SCRIPT_COMMAND_NEXT,
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REG_SCRIPT_COMMAND_END,
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};
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enum {
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REG_SCRIPT_TYPE_PCI,
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REG_SCRIPT_TYPE_IO,
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REG_SCRIPT_TYPE_MMIO,
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REG_SCRIPT_TYPE_RES,
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REG_SCRIPT_TYPE_IOSF,
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};
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enum {
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REG_SCRIPT_SIZE_8,
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REG_SCRIPT_SIZE_16,
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REG_SCRIPT_SIZE_32,
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};
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struct reg_script {
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uint32_t command;
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uint32_t type;
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uint32_t size;
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uint32_t reg;
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uint32_t mask;
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uint32_t value;
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uint32_t timeout;
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union {
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uint32_t id;
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const struct reg_script *next;
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device_t dev;
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unsigned int res_index;
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};
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};
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/* Internal helper Macros. */
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#define _REG_SCRIPT_ENCODE_RAW(cmd_, type_, size_, reg_, \
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mask_, value_, timeout_, id_) \
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{ .command = cmd_, \
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.type = type_, \
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.size = size_, \
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.reg = reg_, \
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.mask = mask_, \
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.value = value_, \
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.timeout = timeout_, \
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.id = id_, \
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}
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#define _REG_SCRIPT_ENCODE_RES(cmd_, type_, res_index_, size_, reg_, \
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mask_, value_, timeout_) \
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{ .command = cmd_, \
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.type = type_, \
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.size = size_, \
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.reg = reg_, \
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.mask = mask_, \
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.value = value_, \
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.timeout = timeout_, \
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.res_index = res_index_, \
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}
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/*
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* PCI
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*/
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#define REG_SCRIPT_PCI(cmd_, bits_, reg_, mask_, value_, timeout_) \
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_REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, \
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REG_SCRIPT_TYPE_PCI, \
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REG_SCRIPT_SIZE_##bits_, \
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reg_, mask_, value_, timeout_, 0)
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#define REG_PCI_READ8(reg_) \
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REG_SCRIPT_PCI(READ, 8, reg_, 0, 0, 0)
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#define REG_PCI_READ16(reg_) \
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REG_SCRIPT_PCI(READ, 16, reg_, 0, 0, 0)
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#define REG_PCI_READ32(reg_) \
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REG_SCRIPT_PCI(READ, 32, reg_, 0, 0, 0)
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#define REG_PCI_WRITE8(reg_, value_) \
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REG_SCRIPT_PCI(WRITE, 8, reg_, 0, value_, 0)
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#define REG_PCI_WRITE16(reg_, value_) \
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REG_SCRIPT_PCI(WRITE, 16, reg_, 0, value_, 0)
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#define REG_PCI_WRITE32(reg_, value_) \
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REG_SCRIPT_PCI(WRITE, 32, reg_, 0, value_, 0)
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#define REG_PCI_RMW8(reg_, mask_, value_) \
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REG_SCRIPT_PCI(RMW, 8, reg_, mask_, value_, 0)
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#define REG_PCI_RMW16(reg_, mask_, value_) \
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REG_SCRIPT_PCI(RMW, 16, reg_, mask_, value_, 0)
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#define REG_PCI_RMW32(reg_, mask_, value_) \
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REG_SCRIPT_PCI(RMW, 32, reg_, mask_, value_, 0)
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#define REG_PCI_OR8(reg_, value_) \
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REG_SCRIPT_PCI(RMW, 8, reg_, 0xff, value_, 0)
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#define REG_PCI_OR16(reg_, value_) \
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REG_SCRIPT_PCI(RMW, 16, reg_, 0xffff, value_, 0)
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#define REG_PCI_OR32(reg_, value_) \
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REG_SCRIPT_PCI(RMW, 32, reg_, 0xffffffff, value_, 0)
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#define REG_PCI_POLL8(reg_, mask_, value_, timeout_) \
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REG_SCRIPT_PCI(POLL, 8, reg_, mask_, value_, timeout_)
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#define REG_PCI_POLL16(reg_, mask_, value_, timeout_) \
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REG_SCRIPT_PCI(POLL, 16, reg_, mask_, value_, timeout_)
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#define REG_PCI_POLL32(reg_, mask_, value_, timeout_) \
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REG_SCRIPT_PCI(POLL, 32, reg_, mask_, value_, timeout_)
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/*
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* Legacy IO
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*/
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#define REG_SCRIPT_IO(cmd_, bits_, reg_, mask_, value_, timeout_) \
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_REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, \
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REG_SCRIPT_TYPE_IO, \
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REG_SCRIPT_SIZE_##bits_, \
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reg_, mask_, value_, timeout_, 0)
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#define REG_IO_READ8(reg_) \
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REG_SCRIPT_IO(READ, 8, reg_, 0, 0, 0)
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#define REG_IO_READ16(reg_) \
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REG_SCRIPT_IO(READ, 16, reg_, 0, 0, 0)
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#define REG_IO_READ32(reg_) \
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REG_SCRIPT_IO(READ, 32, reg_, 0, 0, 0)
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#define REG_IO_WRITE8(reg_, value_) \
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REG_SCRIPT_IO(WRITE, 8, reg_, 0, value_, 0)
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#define REG_IO_WRITE16(reg_, value_) \
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REG_SCRIPT_IO(WRITE, 16, reg_, 0, value_, 0)
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#define REG_IO_WRITE32(reg_, value_) \
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REG_SCRIPT_IO(WRITE, 32, reg_, 0, value_, 0)
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#define REG_IO_RMW8(reg_, mask_, value_) \
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REG_SCRIPT_IO(RMW, 8, reg_, mask_, value_, 0)
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#define REG_IO_RMW16(reg_, mask_, value_) \
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REG_SCRIPT_IO(RMW, 16, reg_, mask_, value_, 0)
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#define REG_IO_RMW32(reg_, mask_, value_) \
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REG_SCRIPT_IO(RMW, 32, reg_, mask_, value_, 0)
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#define REG_IO_OR8(reg_, value_) \
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REG_SCRIPT_IO_RMW8(_reg, 0xff, value)
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#define REG_IO_OR16(reg_, value_) \
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REG_SCRIPT_IO_RMW16(_reg, 0xffff, value)
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#define REG_IO_OR32(reg_, value_) \
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REG_SCRIPT_IO_RMW32(_reg, 0xffffffff, value)
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#define REG_IO_POLL8(reg_, mask_, value_, timeout_) \
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REG_SCRIPT_IO(POLL, 8, reg_, mask_, value_, timeout_)
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#define REG_IO_POLL16(reg_, mask_, value_, timeout_) \
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REG_SCRIPT_IO(POLL, 16, reg_, mask_, value_, timeout_)
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#define REG_IO_POLL32(reg_, mask_, value_, timeout_) \
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REG_SCRIPT_IO(POLL, 32, reg_, mask_, value_, timeout_)
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/*
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* Memory Mapped IO
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*/
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#define REG_SCRIPT_MMIO(cmd_, bits_, reg_, mask_, value_, timeout_) \
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_REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, \
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REG_SCRIPT_TYPE_MMIO, \
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REG_SCRIPT_SIZE_##bits_, \
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reg_, mask_, value_, timeout_, 0)
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#define REG_MMIO_READ8(reg_) \
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REG_SCRIPT_MMIO(READ, 8, reg_, 0, 0, 0)
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#define REG_MMIO_READ16(reg_) \
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REG_SCRIPT_MMIO(READ, 16, reg_, 0, 0, 0)
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#define REG_MMIO_READ32(reg_) \
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REG_SCRIPT_MMIO(READ, 32, reg_, 0, 0, 0)
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#define REG_MMIO_WRITE8(reg_, value_) \
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REG_SCRIPT_MMIO(WRITE, 8, reg_, 0, value_, 0)
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#define REG_MMIO_WRITE16(reg_, value_) \
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REG_SCRIPT_MMIO(WRITE, 16, reg_, 0, value_, 0)
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#define REG_MMIO_WRITE32(reg_, value_) \
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REG_SCRIPT_MMIO(WRITE, 32, reg_, 0, value_, 0)
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#define REG_MMIO_RMW8(reg_, mask_, value_) \
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REG_SCRIPT_MMIO(RMW, 8, reg_, mask_, value_, 0)
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#define REG_MMIO_RMW16(reg_, mask_, value_) \
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REG_SCRIPT_MMIO(RMW, 16, reg_, mask_, value_, 0)
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#define REG_MMIO_RMW32(reg_, mask_, value_) \
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REG_SCRIPT_MMIO(RMW, 32, reg_, mask_, value_, 0)
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#define REG_MMIO_OR8(reg_, value_) \
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REG_MMIO_RMW8(reg_, 0xff, value_)
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#define REG_MMIO_OR16(reg_, value_) \
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REG_MMIO_RMW16(reg_, 0xffff, value_)
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#define REG_MMIO_OR32(reg_, value_) \
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REG_MMIO_RMW32(reg_, 0xffffffff, value_)
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#define REG_MMIO_POLL8(reg_, mask_, value_, timeout_) \
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REG_SCRIPT_MMIO(POLL, 8, reg_, mask_, value_, timeout_)
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#define REG_MMIO_POLL16(reg_, mask_, value_, timeout_) \
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REG_SCRIPT_MMIO(POLL, 16, reg_, mask_, value_, timeout_)
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#define REG_MMIO_POLL32(reg_, mask_, value_, timeout_) \
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REG_SCRIPT_MMIO(POLL, 32, reg_, mask_, value_, timeout_)
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/*
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* Access through a device's resource such as a Base Address Register (BAR)
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*/
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#define REG_SCRIPT_RES(cmd_, bits_, bar_, reg_, mask_, value_, timeout_) \
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_REG_SCRIPT_ENCODE_RES(REG_SCRIPT_COMMAND_##cmd_, \
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REG_SCRIPT_TYPE_RES, bar_, \
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REG_SCRIPT_SIZE_##bits_, \
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reg_, mask_, value_, timeout_)
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#define REG_RES_READ8(bar_, reg_) \
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REG_SCRIPT_RES(READ, 8, bar_, reg_, 0, 0, 0)
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#define REG_RES_READ16(bar_, reg_) \
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REG_SCRIPT_RES(READ, 16, bar_, reg_, 0, 0, 0)
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#define REG_RES_READ32(bar_, reg_) \
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REG_SCRIPT_RES(READ, 32, bar_, reg_, 0, 0, 0)
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#define REG_RES_WRITE8(bar_, reg_, value_) \
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REG_SCRIPT_RES(WRITE, 8, bar_, reg_, 0, value_, 0)
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#define REG_RES_WRITE16(bar_, reg_, value_) \
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REG_SCRIPT_RES(WRITE, 16, bar_, reg_, 0, value_, 0)
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#define REG_RES_WRITE32(bar_, reg_, value_) \
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REG_SCRIPT_RES(WRITE, 32, bar_, reg_, 0, value_, 0)
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#define REG_RES_RMW8(bar_, reg_, mask_, value_) \
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REG_SCRIPT_RES(RMW, 8, bar_, reg_, mask_, value_, 0)
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#define REG_RES_RMW16(bar_, reg_, mask_, value_) \
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REG_SCRIPT_RES(RMW, 16, bar_, reg_, mask_, value_, 0)
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#define REG_RES_RMW32(bar_, reg_, mask_, value_) \
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REG_SCRIPT_RES(RMW, 32, bar_, reg_, mask_, value_, 0)
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#define REG_RES_OR8(bar_, reg_, value_) \
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REG_RES_RMW8(bar_, reg_, 0xff, value_)
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#define REG_RES_OR16(bar_, reg_, value_) \
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REG_RES_RMW16(bar_, reg_, 0xffff, value_)
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#define REG_RES_OR32(bar_, reg_, value_) \
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REG_RES_RMW32(bar_, reg_, 0xffffffff, value_)
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#define REG_RES_POLL8(bar_, reg_, mask_, value_, timeout_) \
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REG_SCRIPT_RES(POLL, 8, bar_, reg_, mask_, value_, timeout_)
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#define REG_RES_POLL16(bar_, reg_, mask_, value_, timeout_) \
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REG_SCRIPT_RES(POLL, 16, bar_, reg_, mask_, value_, timeout_)
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#define REG_RES_POLL32(bar_, reg_, mask_, value_, timeout_) \
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REG_SCRIPT_RES(POLL, 32, bar_, reg_, mask_, value_, timeout_)
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/*
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* IO Sideband Function
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*/
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#define REG_SCRIPT_IOSF(cmd_, unit_, reg_, mask_, value_, timeout_) \
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_REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, \
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REG_SCRIPT_TYPE_IOSF, \
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REG_SCRIPT_SIZE_32, \
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reg_, mask_, value_, timeout_, unit_)
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#define REG_IOSF_READ(unit_, reg_) \
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REG_SCRIPT_IOSF(READ, unit_, reg_, 0, 0, 0)
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#define REG_IOSF_WRITE(unit_, reg_, value_) \
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REG_SCRIPT_IOSF(WRITE, unit_, reg_, 0, value_, 0)
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#define REG_IOSF_RMW(unit_, reg_, mask_, value_) \
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REG_SCRIPT_IOSF(RMW, unit_, reg_, mask_, value_, 0)
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#define REG_IOSF_OR(unit_, reg_, value_) \
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REG_IOSF_RMW(unit_, reg_, 0xffffffff, value_)
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#define REG_IOSF_POLL(unit_, reg_, mask_, value_, timeout_) \
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REG_SCRIPT_IOSF(POLL, unit_, reg_, mask_, value_, timeout_)
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/*
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* Chain to another table.
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*/
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#define REG_SCRIPT_NEXT(next_) \
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{ .command = REG_SCRIPT_COMMAND_NEXT, \
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.next = next_, \
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}
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/*
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* Set current device
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*/
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#define REG_SCRIPT_SET_DEV(dev_) \
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{ .command = REG_SCRIPT_COMMAND_SET_DEV, \
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.dev = dev_, \
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}
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/*
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* Last script entry. All tables need to end with REG_SCRIPT_END.
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*/
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#define REG_SCRIPT_END \
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_REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_END, 0, 0, 0, 0, 0, 0, 0)
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void reg_script_run(const struct reg_script *script);
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#endif /* REG_SCRIPT_H */
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@ -110,6 +110,8 @@ ramstage-y += cbmem_info.c
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ramstage-y += hexdump.c
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romstage-y += hexdump.c
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ramstage-$(CONFIG_REG_SCRIPT) += reg_script.c
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romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += ramstage_cache.c
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ifneq ($(CONFIG_HAVE_ARCH_MEMSET),y)
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@ -0,0 +1,418 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2013 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
|
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
|
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <arch/io.h>
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#include <console/console.h>
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#include <delay.h>
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#include <device/device.h>
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#include <device/resource.h>
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#include <device/pci.h>
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#include <stdint.h>
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#include <reg_script.h>
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#if CONFIG_SOC_INTEL_BAYTRAIL
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#include <baytrail/iosf.h>
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#endif
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#define POLL_DELAY 100 /* 100us */
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#if defined(__PRE_RAM__)
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#define EMPTY_DEV 0
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#else
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#define EMPTY_DEV NULL
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#endif
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struct reg_script_context {
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device_t dev;
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struct resource *res;
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const struct reg_script *step;
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};
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static inline void reg_script_set_dev(struct reg_script_context *ctx,
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device_t dev)
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{
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ctx->dev = dev;
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ctx->res = NULL;
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||||
}
|
||||
|
||||
static inline void reg_script_set_step(struct reg_script_context *ctx,
|
||||
const struct reg_script *step)
|
||||
{
|
||||
ctx->step = step;
|
||||
}
|
||||
|
||||
static inline const struct reg_script *
|
||||
reg_script_get_step(struct reg_script_context *ctx)
|
||||
{
|
||||
return ctx->step;
|
||||
}
|
||||
|
||||
static struct resource *reg_script_get_resource(struct reg_script_context *ctx)
|
||||
{
|
||||
#if defined(__PRE_RAM__)
|
||||
return NULL;
|
||||
#else
|
||||
struct resource *res;
|
||||
const struct reg_script *step = reg_script_get_step(ctx);
|
||||
|
||||
res = ctx->res;
|
||||
|
||||
if (res != NULL && res->index == step->res_index)
|
||||
return res;
|
||||
|
||||
res = find_resource(ctx->dev, step->res_index);
|
||||
ctx->res = res;
|
||||
return res;
|
||||
#endif
|
||||
}
|
||||
|
||||
static uint32_t reg_script_read_pci(struct reg_script_context *ctx)
|
||||
{
|
||||
const struct reg_script *step = reg_script_get_step(ctx);
|
||||
|
||||
switch (step->size) {
|
||||
case REG_SCRIPT_SIZE_8:
|
||||
return pci_read_config8(ctx->dev, step->reg);
|
||||
case REG_SCRIPT_SIZE_16:
|
||||
return pci_read_config16(ctx->dev, step->reg);
|
||||
case REG_SCRIPT_SIZE_32:
|
||||
return pci_read_config32(ctx->dev, step->reg);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void reg_script_write_pci(struct reg_script_context *ctx)
|
||||
{
|
||||
const struct reg_script *step = reg_script_get_step(ctx);
|
||||
|
||||
switch (step->size) {
|
||||
case REG_SCRIPT_SIZE_8:
|
||||
pci_write_config8(ctx->dev, step->reg, step->value);
|
||||
break;
|
||||
case REG_SCRIPT_SIZE_16:
|
||||
pci_write_config16(ctx->dev, step->reg, step->value);
|
||||
break;
|
||||
case REG_SCRIPT_SIZE_32:
|
||||
pci_write_config32(ctx->dev, step->reg, step->value);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static uint32_t reg_script_read_io(struct reg_script_context *ctx)
|
||||
{
|
||||
const struct reg_script *step = reg_script_get_step(ctx);
|
||||
|
||||
switch (step->size) {
|
||||
case REG_SCRIPT_SIZE_8:
|
||||
return inb(step->reg);
|
||||
case REG_SCRIPT_SIZE_16:
|
||||
return inw(step->reg);
|
||||
case REG_SCRIPT_SIZE_32:
|
||||
return inl(step->reg);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void reg_script_write_io(struct reg_script_context *ctx)
|
||||
{
|
||||
const struct reg_script *step = reg_script_get_step(ctx);
|
||||
|
||||
switch (step->size) {
|
||||
case REG_SCRIPT_SIZE_8:
|
||||
outb(step->value, step->reg);
|
||||
break;
|
||||
case REG_SCRIPT_SIZE_16:
|
||||
outw(step->value, step->reg);
|
||||
break;
|
||||
case REG_SCRIPT_SIZE_32:
|
||||
outl(step->value, step->reg);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static uint32_t reg_script_read_mmio(struct reg_script_context *ctx)
|
||||
{
|
||||
const struct reg_script *step = reg_script_get_step(ctx);
|
||||
|
||||
switch (step->size) {
|
||||
case REG_SCRIPT_SIZE_8:
|
||||
return read8(step->reg);
|
||||
case REG_SCRIPT_SIZE_16:
|
||||
return read16(step->reg);
|
||||
case REG_SCRIPT_SIZE_32:
|
||||
return read32(step->reg);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void reg_script_write_mmio(struct reg_script_context *ctx)
|
||||
{
|
||||
const struct reg_script *step = reg_script_get_step(ctx);
|
||||
|
||||
switch (step->size) {
|
||||
case REG_SCRIPT_SIZE_8:
|
||||
write8(step->reg, step->value);
|
||||
break;
|
||||
case REG_SCRIPT_SIZE_16:
|
||||
write16(step->reg, step->value);
|
||||
break;
|
||||
case REG_SCRIPT_SIZE_32:
|
||||
write32(step->reg, step->value);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static uint32_t reg_script_read_res(struct reg_script_context *ctx)
|
||||
{
|
||||
struct resource *res;
|
||||
uint32_t val = 0;
|
||||
const struct reg_script *step = reg_script_get_step(ctx);
|
||||
|
||||
res = reg_script_get_resource(ctx);
|
||||
|
||||
if (res == NULL)
|
||||
return val;
|
||||
|
||||
if (res->flags & IORESOURCE_IO) {
|
||||
const struct reg_script io_step = {
|
||||
.size = step->size,
|
||||
.reg = res->base + step->reg,
|
||||
};
|
||||
reg_script_set_step(ctx, &io_step);
|
||||
val = reg_script_read_io(ctx);
|
||||
}
|
||||
else if (res->flags & IORESOURCE_MEM) {
|
||||
const struct reg_script mmio_step = {
|
||||
.size = step->size,
|
||||
.reg = res->base + step->reg,
|
||||
};
|
||||
reg_script_set_step(ctx, &mmio_step);
|
||||
val = reg_script_read_mmio(ctx);
|
||||
}
|
||||
reg_script_set_step(ctx, step);
|
||||
return val;
|
||||
}
|
||||
|
||||
static void reg_script_write_res(struct reg_script_context *ctx)
|
||||
{
|
||||
struct resource *res;
|
||||
const struct reg_script *step = reg_script_get_step(ctx);
|
||||
|
||||
res = reg_script_get_resource(ctx);
|
||||
|
||||
if (res == NULL)
|
||||
return;
|
||||
|
||||
if (res->flags & IORESOURCE_IO) {
|
||||
const struct reg_script io_step = {
|
||||
.size = step->size,
|
||||
.reg = res->base + step->reg,
|
||||
.value = step->value,
|
||||
};
|
||||
reg_script_set_step(ctx, &io_step);
|
||||
reg_script_write_io(ctx);
|
||||
}
|
||||
else if (res->flags & IORESOURCE_MEM) {
|
||||
const struct reg_script mmio_step = {
|
||||
.size = step->size,
|
||||
.reg = res->base + step->reg,
|
||||
.value = step->value,
|
||||
};
|
||||
reg_script_set_step(ctx, &mmio_step);
|
||||
reg_script_write_mmio(ctx);
|
||||
}
|
||||
reg_script_set_step(ctx, step);
|
||||
}
|
||||
|
||||
static uint32_t reg_script_read_iosf(struct reg_script_context *ctx)
|
||||
{
|
||||
#if CONFIG_SOC_INTEL_BAYTRAIL
|
||||
const struct reg_script *step = reg_script_get_step(ctx);
|
||||
|
||||
switch (step->id) {
|
||||
case IOSF_PORT_BUNIT:
|
||||
return iosf_bunit_read(step->reg);
|
||||
case IOSF_PORT_DUNIT_CH0:
|
||||
return iosf_dunit_ch0_read(step->reg);
|
||||
case IOSF_PORT_PMC:
|
||||
return iosf_punit_read(step->reg);
|
||||
case IOSF_PORT_USBPHY:
|
||||
return iosf_usbphy_read(step->reg);
|
||||
case IOSF_PORT_USHPHY:
|
||||
return iosf_ushphy_read(step->reg);
|
||||
}
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void reg_script_write_iosf(struct reg_script_context *ctx)
|
||||
{
|
||||
#if CONFIG_SOC_INTEL_BAYTRAIL
|
||||
const struct reg_script *step = reg_script_get_step(ctx);
|
||||
|
||||
switch (step->id) {
|
||||
case IOSF_PORT_BUNIT:
|
||||
iosf_bunit_write(step->reg, step->value);
|
||||
break;
|
||||
case IOSF_PORT_DUNIT_CH0:
|
||||
iosf_dunit_write(step->reg, step->value);
|
||||
break;
|
||||
case IOSF_PORT_PMC:
|
||||
iosf_punit_write(step->reg, step->value);
|
||||
break;
|
||||
case IOSF_PORT_USBPHY:
|
||||
iosf_usbphy_write(step->reg, step->value);
|
||||
break;
|
||||
case IOSF_PORT_USHPHY:
|
||||
iosf_ushphy_write(step->reg, step->value);
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
static uint32_t reg_script_read(struct reg_script_context *ctx)
|
||||
{
|
||||
const struct reg_script *step = reg_script_get_step(ctx);
|
||||
|
||||
switch (step->type) {
|
||||
case REG_SCRIPT_TYPE_PCI:
|
||||
return reg_script_read_pci(ctx);
|
||||
case REG_SCRIPT_TYPE_IO:
|
||||
return reg_script_read_io(ctx);
|
||||
case REG_SCRIPT_TYPE_MMIO:
|
||||
return reg_script_read_mmio(ctx);
|
||||
case REG_SCRIPT_TYPE_RES:
|
||||
return reg_script_read_res(ctx);
|
||||
case REG_SCRIPT_TYPE_IOSF:
|
||||
return reg_script_read_iosf(ctx);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void reg_script_write(struct reg_script_context *ctx)
|
||||
{
|
||||
const struct reg_script *step = reg_script_get_step(ctx);
|
||||
|
||||
switch (step->type) {
|
||||
case REG_SCRIPT_TYPE_PCI:
|
||||
reg_script_write_pci(ctx);
|
||||
break;
|
||||
case REG_SCRIPT_TYPE_IO:
|
||||
reg_script_write_io(ctx);
|
||||
break;
|
||||
case REG_SCRIPT_TYPE_MMIO:
|
||||
reg_script_write_mmio(ctx);
|
||||
break;
|
||||
case REG_SCRIPT_TYPE_RES:
|
||||
reg_script_write_res(ctx);
|
||||
break;
|
||||
case REG_SCRIPT_TYPE_IOSF:
|
||||
reg_script_write_iosf(ctx);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static void reg_script_rmw(struct reg_script_context *ctx)
|
||||
{
|
||||
uint32_t value;
|
||||
const struct reg_script *step = reg_script_get_step(ctx);
|
||||
struct reg_script write_step = *step;
|
||||
|
||||
value = reg_script_read(ctx);
|
||||
value &= step->mask;
|
||||
value |= step->value;
|
||||
write_step.value = value;
|
||||
reg_script_set_step(ctx, &write_step);
|
||||
reg_script_write(ctx);
|
||||
reg_script_set_step(ctx, step);
|
||||
}
|
||||
|
||||
/* In order to easily chain scripts together handle the REG_SCRIPT_COMMAND_NEXT
|
||||
* as recursive call with a new context that has the same dev and resource
|
||||
* as the previous one. That will run to completion and then move on to the
|
||||
* next step of the previous context. */
|
||||
static void reg_script_run_next(struct reg_script_context *ctx,
|
||||
const struct reg_script *step);
|
||||
|
||||
static void reg_script_run_with_context(struct reg_script_context *ctx)
|
||||
{
|
||||
uint32_t value = 0, try;
|
||||
|
||||
while (1) {
|
||||
const struct reg_script *step = reg_script_get_step(ctx);
|
||||
|
||||
if (step->command == REG_SCRIPT_COMMAND_END)
|
||||
break;
|
||||
|
||||
switch (step->command) {
|
||||
case REG_SCRIPT_COMMAND_READ:
|
||||
(void)reg_script_read(ctx);
|
||||
break;
|
||||
case REG_SCRIPT_COMMAND_WRITE:
|
||||
reg_script_write(ctx);
|
||||
break;
|
||||
case REG_SCRIPT_COMMAND_RMW:
|
||||
reg_script_rmw(ctx);
|
||||
break;
|
||||
case REG_SCRIPT_COMMAND_POLL:
|
||||
for (try = 0; try < step->timeout; try += POLL_DELAY) {
|
||||
value = reg_script_read(ctx) & step->mask;
|
||||
if (value == step->value)
|
||||
break;
|
||||
udelay(POLL_DELAY);
|
||||
}
|
||||
if (try >= step->timeout)
|
||||
printk(BIOS_WARNING, "%s: POLL timeout waiting "
|
||||
"for 0x%08x to be 0x%08x, got 0x%08x\n",
|
||||
__func__, step->reg, step->value, value);
|
||||
break;
|
||||
case REG_SCRIPT_COMMAND_SET_DEV:
|
||||
reg_script_set_dev(ctx, step->dev);
|
||||
break;
|
||||
case REG_SCRIPT_COMMAND_NEXT:
|
||||
reg_script_run_next(ctx, step->next);
|
||||
break;
|
||||
default:
|
||||
printk(BIOS_WARNING, "Invalid command: %08x\n",
|
||||
step->command);
|
||||
break;
|
||||
}
|
||||
|
||||
reg_script_set_step(ctx, step + 1);
|
||||
}
|
||||
}
|
||||
|
||||
static void reg_script_run_next(struct reg_script_context *prev_ctx,
|
||||
const struct reg_script *step)
|
||||
{
|
||||
struct reg_script_context ctx;
|
||||
|
||||
/* Use prev context as a basis but start at a new step. */
|
||||
ctx = *prev_ctx;
|
||||
reg_script_set_step(&ctx, step);
|
||||
reg_script_run_with_context(&ctx);
|
||||
}
|
||||
|
||||
void reg_script_run(const struct reg_script *step)
|
||||
{
|
||||
struct reg_script_context ctx;
|
||||
|
||||
reg_script_set_dev(&ctx, EMPTY_DEV);
|
||||
reg_script_set_step(&ctx, step);
|
||||
reg_script_run_with_context(&ctx);
|
||||
}
|
||||
Loading…
Reference in New Issue