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AMD {SoC, AGESA, binaryPI}: Don't use both of _ADR and _HID 

PCI devices starting from 18 are processor configuration devices for each
node and are not a bus itself.

According to ACPI specification 6.3 section 6.1.5:

"... _HID object must be used to describe any device that will be
enumerated by OSPM. OSPM only enumerates a device when no bus enumerator
can detect the device ID. ... Use the _ADR object to describe devices
enumerated by bus enumerators other than OSPM."

PCI device 18 with its functions has a standard enumerator, which is PCI
enumerator so it needs a _ADR. Create a separate ACPI device for the
processor configuration space. This fixes the ACPI compliance problem
from CB:36318.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ie7b45ce8d9e4fdd80d90752bf51bba4d30041507
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37835
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Michał Żygowski 2019-12-19 12:56:21 +01:00 committed by Patrick Georgi
parent a87a741b41
commit 727ac0d263
8 changed files with 32 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
src/northbridge/amd/agesa/family14/acpi/northbridge.asl
View File

@ -18,13 +18,16 @@ External (TOM1)
External (TOM2) External (TOM2)
Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */
Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */
Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
/* Describe the Northbridge devices */ /* Describe the Northbridge devices */
Device(AMRT) { Device(AMRT) {
Name(_ADR, 0x00000000) Name(_ADR, 0x00000000)
} /* end AMRT */ } /* end AMRT */
Device(PCSD) { /* Processor configuration space devices */
Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
}
/* The internal GFX bridge */ /* The internal GFX bridge */
Device(AGPB) { Device(AGPB) {
Name(_ADR, 0x00010000) Name(_ADR, 0x00010000)

5
src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl
View File

@ -17,7 +17,6 @@
External (TOM1) External (TOM1)
External (TOM2) External (TOM2)
Name(_HID, EISAID("PNP0A03")) /* PCI Express Root Bridge */ Name(_HID, EISAID("PNP0A03")) /* PCI Express Root Bridge */
Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
/* Describe the Northbridge devices */ /* Describe the Northbridge devices */
@ -45,6 +44,10 @@ Device(AMRT) {
Name(_ADR, 0x00000000) Name(_ADR, 0x00000000)
} /* end AMRT */ } /* end AMRT */
Device(PCSD) { /* Processor configuration space devices */
Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
}
/* Dev2 is also an external GFX bridge */ /* Dev2 is also an external GFX bridge */
Device(PBR2) { Device(PBR2) {
Name(_ADR, 0x00020000) Name(_ADR, 0x00020000)

5
src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl
View File

@ -18,7 +18,6 @@ External (TOM1)
External (TOM2) External (TOM2)
Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */
Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */
Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
/* Describe the Northbridge devices */ /* Describe the Northbridge devices */
@ -45,6 +44,10 @@ Device(AMRT) {
Name(_ADR, 0x00000000) Name(_ADR, 0x00000000)
} /* end AMRT */ } /* end AMRT */
Device(PCSD) { /* Processor configuration space devices */
Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
}
/* Gpp 0 */ /* Gpp 0 */
Device(PBR4) { Device(PBR4) {
Name(_ADR, 0x00020001) Name(_ADR, 0x00020001)

5
src/northbridge/amd/pi/00630F01/acpi/northbridge.asl
View File

@ -17,7 +17,6 @@
External (TOM1) External (TOM1)
External (TOM2) External (TOM2)
Name(_HID, EISAID("PNP0A03")) /* PCI Express Root Bridge */ Name(_HID, EISAID("PNP0A03")) /* PCI Express Root Bridge */
Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
/* Describe the Northbridge devices */ /* Describe the Northbridge devices */
@ -45,6 +44,10 @@ Device(AMRT) {
Name(_ADR, 0x00000000) Name(_ADR, 0x00000000)
} /* end AMRT */ } /* end AMRT */
Device(PCSD) { /* Processor configuration space devices */
Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
}
/* Dev2 is also an external GFX bridge */ /* Dev2 is also an external GFX bridge */
Device(PBR2) { Device(PBR2) {
Name(_ADR, 0x00020000) Name(_ADR, 0x00020000)

5
src/northbridge/amd/pi/00660F01/acpi/northbridge.asl
View File

@ -18,7 +18,6 @@ External (TOM1)
External (TOM2) External (TOM2)
Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */
Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */
Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
/* Describe the Northbridge devices */ /* Describe the Northbridge devices */
@ -45,6 +44,10 @@ Device(AMRT) {
Name(_ADR, 0x00000000) Name(_ADR, 0x00000000)
} /* end AMRT */ } /* end AMRT */
Device(PCSD) { /* Processor configuration space devices */
Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
}
/* Gpp 0 */ /* Gpp 0 */
Device(PBR4) { Device(PBR4) {
Name(_ADR, 0x00020001) Name(_ADR, 0x00020001)

5
src/northbridge/amd/pi/00730F01/acpi/northbridge.asl
View File

@ -18,7 +18,6 @@ External (TOM1)
External (TOM2) External (TOM2)
Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */
Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */
Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
/* Describe the Northbridge devices */ /* Describe the Northbridge devices */
@ -45,6 +44,10 @@ Device(AMRT) {
Name(_ADR, 0x00000000) Name(_ADR, 0x00000000)
} /* end AMRT */ } /* end AMRT */
Device(PCSD) { /* Processor configuration space devices */
Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
}
/* Gpp 0 */ /* Gpp 0 */
Device(PBR4) { Device(PBR4) {
Name(_ADR, 0x00020001) Name(_ADR, 0x00020001)

5
src/soc/amd/picasso/acpi/northbridge.asl
View File

@ -19,7 +19,6 @@ External (TOM1)
External (TOM2) External (TOM2)
Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */
Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */
Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
/* Describe the Northbridge devices */ /* Describe the Northbridge devices */
@ -46,6 +45,10 @@ Device(AMRT) {
Name(_ADR, 0x00000000) Name(_ADR, 0x00000000)
} /* end AMRT */ } /* end AMRT */
Device(PCSD) { /* Processor configuration space devices */
Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
}
/* Internal Graphics */ /* Internal Graphics */
Device(IGFX) { Device(IGFX) {
Name(_ADR, 0x00010000) Name(_ADR, 0x00010000)

5
src/soc/amd/stoneyridge/acpi/northbridge.asl
View File

@ -19,7 +19,6 @@ External (TOM1)
External (TOM2) External (TOM2)
Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */
Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */
Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
/* Describe the Northbridge devices */ /* Describe the Northbridge devices */
@ -46,6 +45,10 @@ Device(AMRT) {
Name(_ADR, 0x00000000) Name(_ADR, 0x00000000)
} /* end AMRT */ } /* end AMRT */
Device(PCSD) { /* Processor configuration space devices */
Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
}
/* Internal Graphics */ /* Internal Graphics */
Device(IGFX) { Device(IGFX) {
Name(_ADR, 0x00010000) Name(_ADR, 0x00010000)