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mb/google/brya/var/felwinter: Correct garage wake event 

Eject event is high. Set wake event to active high. The polarity of the SCI and the wakeup_event_action for the pen ejection feature were both
backwards, and was causing the system to fail to enter sleep states
because the event was always asserted.

BUG=b:208937710
TEST=only release switch can wake system.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I568e9175c7a66599f7a525c32e4def7a79b55a0a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Eric Lai 2021-12-03 17:38:52 +08:00 committed by Patrick Georgi
parent 7d925c5fb8
commit 727c7bf221
2 changed files with 2 additions and 2 deletions
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2
src/mainboard/google/brya/variants/felwinter/gpio.c
View File

@ -10,7 +10,7 @@ static const struct pad_config override_gpio_table[] = {
/* A7 : SRCCLK_OE7# ==> PEN_DET_ODL */
PAD_CFG_GPI_GPIO_DRIVER(GPP_A7, NONE, DEEP),
/* A8 : SRCCLKREQ7# ==> PEN_DET_ODL */
PAD_CFG_GPI_SCI_LOW(GPP_A8, NONE, DEEP, EDGE_SINGLE),
PAD_CFG_GPI_SCI_HIGH(GPP_A8, NONE, DEEP, EDGE_SINGLE),
/* B3 : PROC_GP2 ==> NC */
PAD_NC(GPP_B3, NONE),
/* B5 : ISH_I2C0_SDA ==> NC */

2
src/mainboard/google/brya/variants/felwinter/overridetree.cb
View File

@ -264,7 +264,7 @@ chip soc/intel/alderlake
register "gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A7)"
register "key.wake_gpe" = "GPE0_DW0_08"
register "key.wakeup_route" = "WAKEUP_ROUTE_SCI"
register "key.wakeup_event_action" = "EV_ACT_DEASSERTED"
register "key.wakeup_event_action" = "EV_ACT_ASSERTED"
register "key.dev_name" = ""EJCT""
register "key.linux_code" = "SW_PEN_INSERTED"
register "key.linux_input_type" = "EV_SW"