mainboard/hp: Add HP Elitebook 8460p
The code is based on autoport. I'm using a machine with discrete GPU, and gfx.* in devicetree.cb is from 2760p. It can be debug with serial port on dock. Tested: - CPU and memory: i5-2540M, 4G+0 - Arch Linux (Linux 4.11.7, SeaBIOS payload, with ATOM BIOS extracted from vendor UEFI firmware) - USB ports - SD card reader - WLAN - DP display - S3 Change-Id: I9c42723ba240a2e9b46998c1a8a708aebc66c604 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/20501 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Iru Cai
Martin Roth
parent
6f08ef9bda
commit
728d488ab3
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#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2017 Iru Cai <mytbk920423@gmail.com>
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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if BOARD_HP_8460P
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select BOARD_ROMSIZE_KB_8192
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select CPU_INTEL_SOCKET_RPGA989
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select INTEL_INT15
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select NORTHBRIDGE_INTEL_SANDYBRIDGE
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select SANDYBRIDGE_IVYBRIDGE_LVDS
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select SERIRQ_CONTINUOUS_MODE
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select SOUTHBRIDGE_INTEL_BD82X6X
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select SYSTEM_TYPE_LAPTOP
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select USE_NATIVE_RAMINIT
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select MAINBOARD_HAS_LIBGFXINIT
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select GFX_GMA_INTERNAL_IS_LVDS
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select EC_HP_KBC1126
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select SUPERIO_SMSC_LPC47N217
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config HAVE_IFD_BIN
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bool
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default n
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config HAVE_ME_BIN
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bool
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default n
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config MAINBOARD_DIR
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string
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default hp/8460p
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config MAINBOARD_PART_NUMBER
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string
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default "EliteBook 8460p"
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config VGA_BIOS_FILE
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string
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default "pci8086,0116.rom"
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config VGA_BIOS_ID
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string
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default "8086,0116"
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config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
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hex
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default 0x161c
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config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
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hex
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default 0x103c
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config MAX_CPUS
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int
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default 8
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config USBDEBUG_HCD_INDEX
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int
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default 1
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endif
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@ -0,0 +1,2 @@
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config BOARD_HP_8460P
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bool "EliteBook 8460p"
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@ -0,0 +1,18 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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romstage-y += gpio.c
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ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017 Iru Cai <mytbk920423@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <ec/hp/kbc1126/acpi/ec.asl>
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@ -0,0 +1,23 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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Method(_WAK,1)
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{
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Return(Package(){0,0})
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}
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Method(_PTS,1)
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{
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}
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <drivers/pc80/pc/ps2_controller.asl>
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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* Copyright (C) 2014 Vladimir Serbinenko
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <southbridge/intel/bd82x6x/nvs.h>
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void acpi_create_gnvs(global_nvs_t *gnvs)
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{
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/* Disable USB ports in S3 by default */
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gnvs->s3u0 = 0;
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gnvs->s3u1 = 0;
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/* Disable USB ports in S5 by default */
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gnvs->s5u0 = 0;
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gnvs->s5u1 = 0;
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// the lid is open by default.
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gnvs->lids = 1;
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gnvs->tcrt = 100;
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gnvs->tpsv = 90;
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}
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@ -0,0 +1,7 @@
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Category: laptop
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Board URL: https://support.hp.com/us-en/product/HP-EliteBook-8460p-Notebook-PC/5056942
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ROM package: SOIC-8
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ROM protocol: SPI
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ROM socketed: n
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Flashrom support: n
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Release year: 2011
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#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2017 Iru Cai <mytbk920423@gmail.com>
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; either version 2 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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chip northbridge/intel/sandybridge
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register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }"
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register "gfx.link_frequency_270_mhz" = "1"
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register "gfx.ndid" = "3"
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register "gfx.use_spread_spectrum_clock" = "1"
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register "gpu_cpu_backlight" = "0x00000129"
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register "gpu_dp_b_hotplug" = "4"
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register "gpu_dp_c_hotplug" = "4"
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register "gpu_dp_d_hotplug" = "4"
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register "gpu_panel_port_select" = "0"
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register "gpu_panel_power_backlight_off_delay" = "2000"
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register "gpu_panel_power_backlight_on_delay" = "2000"
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register "gpu_panel_power_cycle_delay" = "5"
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register "gpu_panel_power_down_delay" = "230"
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register "gpu_panel_power_up_delay" = "300"
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register "gpu_pch_backlight" = "0x02880288"
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device cpu_cluster 0x0 on
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chip cpu/intel/socket_rPGA989
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device lapic 0x0 on
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end
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end
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chip cpu/intel/model_206ax
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register "c1_acpower" = "1"
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register "c1_battery" = "1"
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register "c2_acpower" = "3"
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register "c2_battery" = "3"
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register "c3_acpower" = "5"
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register "c3_battery" = "5"
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device lapic 0xacac off
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end
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end
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end
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device domain 0x0 on
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device pci 00.0 on # Host bridge
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subsystemid 0x103c 0x161c
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end
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device pci 01.0 on # PCIe Bridge for discrete graphics
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end
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device pci 02.0 on # Internal graphics
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subsystemid 0x103c 0x161c
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end
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chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
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register "c2_latency" = "0x0065"
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register "docking_supported" = "0"
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register "gen1_dec" = "0x007c0201"
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register "gen2_dec" = "0x000c0101"
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register "gen3_dec" = "0x00fcfe01"
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register "gen4_dec" = "0x000402e9"
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register "gpi6_routing" = "2"
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register "p_cnt_throttling_supported" = "1"
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register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }"
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register "pcie_port_coalesce" = "1"
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register "sata_interface_speed_support" = "0x3"
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register "sata_port_map" = "0x3b"
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register "spi_uvscc" = "0x2005"
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register "spi_lvscc" = "0"
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device pci 16.0 on # Management Engine Interface 1
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subsystemid 0x103c 0x161c
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end
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device pci 16.1 off # Management Engine Interface 2
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end
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device pci 16.2 off # Management Engine IDE-R
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end
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device pci 16.3 on # Management Engine KT
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subsystemid 0x103c 0x161c
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end
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device pci 19.0 on # Intel Gigabit Ethernet
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subsystemid 0x103c 0x161c
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end
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device pci 1a.0 on # USB2 EHCI #2
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subsystemid 0x103c 0x161c
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end
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device pci 1b.0 on # High Definition Audio Audio controller
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subsystemid 0x103c 0x161c
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end
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device pci 1c.0 on # PCIe Port #1
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subsystemid 0x103c 0x161c
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end
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device pci 1c.1 on # PCIe Port #2
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subsystemid 0x103c 0x161c
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end
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device pci 1c.2 on # PCIe Port #3
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subsystemid 0x103c 0x161c
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end
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device pci 1c.3 on # PCIe Port #4
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subsystemid 0x103c 0x161c
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end
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device pci 1c.4 off # PCIe Port #5
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end
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device pci 1c.5 off # PCIe Port #6
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end
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device pci 1c.6 off # PCIe Port #7
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end
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device pci 1c.7 on # PCIe Port #8
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subsystemid 0x103c 0x161c
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end
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device pci 1d.0 on # USB2 EHCI #1
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subsystemid 0x103c 0x161c
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end
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device pci 1e.0 off # PCI bridge
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end
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device pci 1f.0 on # LPC bridge PCI-LPC bridge
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subsystemid 0x103c 0x161c
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chip ec/hp/kbc1126
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register "ec_data_port" = "0x60"
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register "ec_cmd_port" = "0x64"
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register "ec_ctrl_reg" = "0xca"
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||||||
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register "ec_fan_ctrl_value" = "0x6b"
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device pnp ff.1 off end
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end # kbc1126
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chip superio/smsc/lpc47n217
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device pnp 4e.3 on # Parallel
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io 0x60 = 0x378
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irq 0x70 = 7
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end
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device pnp 4e.4 on # Com1
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io 0x60 = 0x3f8
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||||||
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irq 0x70 = 4
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||||||
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end
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||||||
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device pnp 4e.5 off # Com2
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||||||
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end
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||||||
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end #chip superio/smsc/lpc47n217
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||||||
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end
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||||||
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device pci 1f.2 on # SATA Controller 1
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subsystemid 0x103c 0x161c
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||||||
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end
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||||||
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device pci 1f.3 off # SMBus
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||||||
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end
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||||||
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device pci 1f.5 off # SATA Controller 2
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||||||
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end
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||||||
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device pci 1f.6 off # Thermal
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||||||
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end
|
||||||
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end
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||||||
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end
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||||||
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end
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@ -0,0 +1,45 @@
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/*
|
||||||
|
* This file is part of the coreboot project.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2007-2009 coresystems GmbH
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; version 2 of the License.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
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||||||
|
#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
|
||||||
|
#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
|
||||||
|
DefinitionBlock(
|
||||||
|
"dsdt.aml",
|
||||||
|
"DSDT",
|
||||||
|
0x03, // DSDT revision: ACPI v3.0
|
||||||
|
"COREv4", // OEM id
|
||||||
|
"COREBOOT", // OEM table id
|
||||||
|
0x20141018 // OEM revision
|
||||||
|
)
|
||||||
|
{
|
||||||
|
// Some generic macros
|
||||||
|
#include "acpi/platform.asl"
|
||||||
|
#include <cpu/intel/model_206ax/acpi/cpu.asl>
|
||||||
|
#include <southbridge/intel/bd82x6x/acpi/platform.asl>
|
||||||
|
/* global NVS and variables. */
|
||||||
|
#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
|
||||||
|
#include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
|
||||||
|
|
||||||
|
Scope (\_SB) {
|
||||||
|
Device (PCI0)
|
||||||
|
{
|
||||||
|
#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
|
||||||
|
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
|
||||||
|
#include <southbridge/intel/bd82x6x/acpi/pch.asl>
|
||||||
|
#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,34 @@
|
||||||
|
--
|
||||||
|
-- Copyright (C) 2017 Iru Cai <mytbk920423@gmail.com>
|
||||||
|
--
|
||||||
|
-- This program is free software; you can redistribute it and/or modify
|
||||||
|
-- it under the terms of the GNU General Public License as published by
|
||||||
|
-- the Free Software Foundation; either version 2 of the License, or
|
||||||
|
-- (at your option) any later version.
|
||||||
|
--
|
||||||
|
-- This program is distributed in the hope that it will be useful,
|
||||||
|
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
-- GNU General Public License for more details.
|
||||||
|
--
|
||||||
|
|
||||||
|
with HW.GFX.GMA;
|
||||||
|
with HW.GFX.GMA.Display_Probing;
|
||||||
|
|
||||||
|
use HW.GFX.GMA;
|
||||||
|
use HW.GFX.GMA.Display_Probing;
|
||||||
|
|
||||||
|
private package GMA.Mainboard is
|
||||||
|
|
||||||
|
ports : constant Port_List :=
|
||||||
|
(DP1,
|
||||||
|
DP2,
|
||||||
|
DP3,
|
||||||
|
HDMI1,
|
||||||
|
HDMI2,
|
||||||
|
HDMI3,
|
||||||
|
Analog,
|
||||||
|
Internal,
|
||||||
|
others => Disabled);
|
||||||
|
|
||||||
|
end GMA.Mainboard;
|
||||||
|
|
@ -0,0 +1,240 @@
|
||||||
|
/*
|
||||||
|
* This file is part of the coreboot project.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2008-2009 coresystems GmbH
|
||||||
|
* Copyright (C) 2014 Vladimir Serbinenko
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; version 2 of
|
||||||
|
* the License.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <southbridge/intel/common/gpio.h>
|
||||||
|
|
||||||
|
static const struct pch_gpio_set1 pch_gpio_set1_mode = {
|
||||||
|
.gpio0 = GPIO_MODE_GPIO,
|
||||||
|
.gpio1 = GPIO_MODE_GPIO,
|
||||||
|
.gpio2 = GPIO_MODE_GPIO,
|
||||||
|
.gpio3 = GPIO_MODE_GPIO,
|
||||||
|
.gpio4 = GPIO_MODE_GPIO,
|
||||||
|
.gpio5 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio6 = GPIO_MODE_GPIO,
|
||||||
|
.gpio7 = GPIO_MODE_GPIO,
|
||||||
|
.gpio8 = GPIO_MODE_GPIO,
|
||||||
|
.gpio9 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio10 = GPIO_MODE_GPIO,
|
||||||
|
.gpio11 = GPIO_MODE_GPIO,
|
||||||
|
.gpio12 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio13 = GPIO_MODE_GPIO,
|
||||||
|
.gpio14 = GPIO_MODE_GPIO,
|
||||||
|
.gpio15 = GPIO_MODE_GPIO,
|
||||||
|
.gpio16 = GPIO_MODE_GPIO,
|
||||||
|
.gpio17 = GPIO_MODE_GPIO,
|
||||||
|
.gpio18 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio19 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio20 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio21 = GPIO_MODE_GPIO,
|
||||||
|
.gpio22 = GPIO_MODE_GPIO,
|
||||||
|
.gpio23 = GPIO_MODE_GPIO,
|
||||||
|
.gpio24 = GPIO_MODE_GPIO,
|
||||||
|
.gpio25 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio26 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio27 = GPIO_MODE_GPIO,
|
||||||
|
.gpio28 = GPIO_MODE_GPIO,
|
||||||
|
.gpio29 = GPIO_MODE_GPIO,
|
||||||
|
.gpio30 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio31 = GPIO_MODE_NATIVE,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct pch_gpio_set1 pch_gpio_set1_direction = {
|
||||||
|
.gpio0 = GPIO_DIR_OUTPUT,
|
||||||
|
.gpio1 = GPIO_DIR_INPUT,
|
||||||
|
.gpio2 = GPIO_DIR_INPUT,
|
||||||
|
.gpio3 = GPIO_DIR_INPUT,
|
||||||
|
.gpio4 = GPIO_DIR_INPUT,
|
||||||
|
.gpio6 = GPIO_DIR_INPUT,
|
||||||
|
.gpio7 = GPIO_DIR_INPUT,
|
||||||
|
.gpio8 = GPIO_DIR_INPUT,
|
||||||
|
.gpio10 = GPIO_DIR_INPUT,
|
||||||
|
.gpio11 = GPIO_DIR_OUTPUT,
|
||||||
|
.gpio13 = GPIO_DIR_INPUT,
|
||||||
|
.gpio14 = GPIO_DIR_INPUT,
|
||||||
|
.gpio15 = GPIO_DIR_INPUT,
|
||||||
|
.gpio16 = GPIO_DIR_INPUT,
|
||||||
|
.gpio17 = GPIO_DIR_OUTPUT,
|
||||||
|
.gpio21 = GPIO_DIR_INPUT,
|
||||||
|
.gpio22 = GPIO_DIR_OUTPUT,
|
||||||
|
.gpio23 = GPIO_DIR_INPUT,
|
||||||
|
.gpio24 = GPIO_DIR_OUTPUT,
|
||||||
|
.gpio27 = GPIO_DIR_OUTPUT,
|
||||||
|
.gpio28 = GPIO_DIR_OUTPUT,
|
||||||
|
.gpio29 = GPIO_DIR_OUTPUT,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct pch_gpio_set1 pch_gpio_set1_level = {
|
||||||
|
.gpio0 = GPIO_LEVEL_LOW,
|
||||||
|
.gpio11 = GPIO_LEVEL_LOW,
|
||||||
|
.gpio17 = GPIO_LEVEL_HIGH,
|
||||||
|
.gpio22 = GPIO_LEVEL_HIGH,
|
||||||
|
.gpio24 = GPIO_LEVEL_HIGH,
|
||||||
|
.gpio27 = GPIO_LEVEL_LOW,
|
||||||
|
.gpio28 = GPIO_LEVEL_LOW,
|
||||||
|
.gpio29 = GPIO_LEVEL_HIGH,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct pch_gpio_set1 pch_gpio_set1_reset = {
|
||||||
|
.gpio24 = GPIO_RESET_RSMRST,
|
||||||
|
.gpio30 = GPIO_RESET_RSMRST,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct pch_gpio_set1 pch_gpio_set1_invert = {
|
||||||
|
.gpio1 = GPIO_INVERT,
|
||||||
|
.gpio3 = GPIO_INVERT,
|
||||||
|
.gpio6 = GPIO_INVERT,
|
||||||
|
.gpio7 = GPIO_INVERT,
|
||||||
|
.gpio10 = GPIO_INVERT,
|
||||||
|
.gpio13 = GPIO_INVERT,
|
||||||
|
.gpio14 = GPIO_INVERT,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct pch_gpio_set1 pch_gpio_set1_blink = {
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct pch_gpio_set2 pch_gpio_set2_mode = {
|
||||||
|
.gpio32 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio33 = GPIO_MODE_GPIO,
|
||||||
|
.gpio34 = GPIO_MODE_GPIO,
|
||||||
|
.gpio35 = GPIO_MODE_GPIO,
|
||||||
|
.gpio36 = GPIO_MODE_GPIO,
|
||||||
|
.gpio37 = GPIO_MODE_GPIO,
|
||||||
|
.gpio38 = GPIO_MODE_GPIO,
|
||||||
|
.gpio39 = GPIO_MODE_GPIO,
|
||||||
|
.gpio40 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio41 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio42 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio43 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio44 = GPIO_MODE_GPIO,
|
||||||
|
.gpio45 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio46 = GPIO_MODE_GPIO,
|
||||||
|
.gpio47 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio48 = GPIO_MODE_GPIO,
|
||||||
|
.gpio49 = GPIO_MODE_GPIO,
|
||||||
|
.gpio50 = GPIO_MODE_GPIO,
|
||||||
|
.gpio51 = GPIO_MODE_GPIO,
|
||||||
|
.gpio52 = GPIO_MODE_GPIO,
|
||||||
|
.gpio53 = GPIO_MODE_GPIO,
|
||||||
|
.gpio54 = GPIO_MODE_GPIO,
|
||||||
|
.gpio55 = GPIO_MODE_GPIO,
|
||||||
|
.gpio56 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio57 = GPIO_MODE_GPIO,
|
||||||
|
.gpio58 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio59 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio60 = GPIO_MODE_GPIO,
|
||||||
|
.gpio61 = GPIO_MODE_GPIO,
|
||||||
|
.gpio62 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio63 = GPIO_MODE_NATIVE,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct pch_gpio_set2 pch_gpio_set2_direction = {
|
||||||
|
.gpio33 = GPIO_DIR_OUTPUT,
|
||||||
|
.gpio34 = GPIO_DIR_INPUT,
|
||||||
|
.gpio35 = GPIO_DIR_OUTPUT,
|
||||||
|
.gpio36 = GPIO_DIR_OUTPUT,
|
||||||
|
.gpio37 = GPIO_DIR_OUTPUT,
|
||||||
|
.gpio38 = GPIO_DIR_INPUT,
|
||||||
|
.gpio39 = GPIO_DIR_INPUT,
|
||||||
|
.gpio44 = GPIO_DIR_INPUT,
|
||||||
|
.gpio46 = GPIO_DIR_INPUT,
|
||||||
|
.gpio48 = GPIO_DIR_INPUT,
|
||||||
|
.gpio49 = GPIO_DIR_OUTPUT,
|
||||||
|
.gpio50 = GPIO_DIR_INPUT,
|
||||||
|
.gpio51 = GPIO_DIR_INPUT,
|
||||||
|
.gpio52 = GPIO_DIR_INPUT,
|
||||||
|
.gpio53 = GPIO_DIR_OUTPUT,
|
||||||
|
.gpio54 = GPIO_DIR_INPUT,
|
||||||
|
.gpio55 = GPIO_DIR_INPUT,
|
||||||
|
.gpio57 = GPIO_DIR_OUTPUT,
|
||||||
|
.gpio60 = GPIO_DIR_OUTPUT,
|
||||||
|
.gpio61 = GPIO_DIR_OUTPUT,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct pch_gpio_set2 pch_gpio_set2_level = {
|
||||||
|
.gpio33 = GPIO_LEVEL_LOW,
|
||||||
|
.gpio35 = GPIO_LEVEL_LOW,
|
||||||
|
.gpio36 = GPIO_LEVEL_LOW,
|
||||||
|
.gpio37 = GPIO_LEVEL_LOW,
|
||||||
|
.gpio49 = GPIO_LEVEL_LOW,
|
||||||
|
.gpio53 = GPIO_LEVEL_HIGH,
|
||||||
|
.gpio57 = GPIO_LEVEL_HIGH,
|
||||||
|
.gpio60 = GPIO_LEVEL_HIGH,
|
||||||
|
.gpio61 = GPIO_LEVEL_HIGH,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct pch_gpio_set2 pch_gpio_set2_reset = {
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct pch_gpio_set3 pch_gpio_set3_mode = {
|
||||||
|
.gpio64 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio65 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio66 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio67 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio68 = GPIO_MODE_GPIO,
|
||||||
|
.gpio69 = GPIO_MODE_GPIO,
|
||||||
|
.gpio70 = GPIO_MODE_GPIO,
|
||||||
|
.gpio71 = GPIO_MODE_GPIO,
|
||||||
|
.gpio72 = GPIO_MODE_GPIO,
|
||||||
|
.gpio73 = GPIO_MODE_GPIO,
|
||||||
|
.gpio74 = GPIO_MODE_GPIO,
|
||||||
|
.gpio75 = GPIO_MODE_NATIVE,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct pch_gpio_set3 pch_gpio_set3_direction = {
|
||||||
|
.gpio68 = GPIO_DIR_OUTPUT,
|
||||||
|
.gpio69 = GPIO_DIR_INPUT,
|
||||||
|
.gpio70 = GPIO_DIR_OUTPUT,
|
||||||
|
.gpio71 = GPIO_DIR_OUTPUT,
|
||||||
|
.gpio72 = GPIO_DIR_OUTPUT,
|
||||||
|
.gpio73 = GPIO_DIR_OUTPUT,
|
||||||
|
.gpio74 = GPIO_DIR_OUTPUT,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct pch_gpio_set3 pch_gpio_set3_level = {
|
||||||
|
.gpio68 = GPIO_LEVEL_HIGH,
|
||||||
|
.gpio70 = GPIO_LEVEL_HIGH,
|
||||||
|
.gpio71 = GPIO_LEVEL_HIGH,
|
||||||
|
.gpio72 = GPIO_LEVEL_LOW,
|
||||||
|
.gpio73 = GPIO_LEVEL_HIGH,
|
||||||
|
.gpio74 = GPIO_LEVEL_HIGH,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct pch_gpio_set3 pch_gpio_set3_reset = {
|
||||||
|
};
|
||||||
|
|
||||||
|
const struct pch_gpio_map mainboard_gpio_map = {
|
||||||
|
.set1 = {
|
||||||
|
.mode = &pch_gpio_set1_mode,
|
||||||
|
.direction = &pch_gpio_set1_direction,
|
||||||
|
.level = &pch_gpio_set1_level,
|
||||||
|
.blink = &pch_gpio_set1_blink,
|
||||||
|
.invert = &pch_gpio_set1_invert,
|
||||||
|
.reset = &pch_gpio_set1_reset,
|
||||||
|
},
|
||||||
|
.set2 = {
|
||||||
|
.mode = &pch_gpio_set2_mode,
|
||||||
|
.direction = &pch_gpio_set2_direction,
|
||||||
|
.level = &pch_gpio_set2_level,
|
||||||
|
.reset = &pch_gpio_set2_reset,
|
||||||
|
},
|
||||||
|
.set3 = {
|
||||||
|
.mode = &pch_gpio_set3_mode,
|
||||||
|
.direction = &pch_gpio_set3_direction,
|
||||||
|
.level = &pch_gpio_set3_level,
|
||||||
|
.reset = &pch_gpio_set3_reset,
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
@ -0,0 +1,67 @@
|
||||||
|
/*
|
||||||
|
* This file is part of the coreboot project.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2008-2009 coresystems GmbH
|
||||||
|
* Copyright (C) 2014 Vladimir Serbinenko
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; version 2 of
|
||||||
|
* the License.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <device/azalia_device.h>
|
||||||
|
|
||||||
|
const u32 cim_verb_data[] = {
|
||||||
|
0x111d7605, /* Codec Vendor / Device ID: IDT */
|
||||||
|
0x103c3588, /* Subsystem ID */
|
||||||
|
|
||||||
|
0x0000000b, /* Number of 4 dword sets */
|
||||||
|
/* NID 0x01: Subsystem ID. */
|
||||||
|
AZALIA_SUBVENDOR(0x0, 0x103c3588),
|
||||||
|
|
||||||
|
/* NID 0x0a. */
|
||||||
|
AZALIA_PIN_CFG(0x0, 0x0a, 0x40f000f0),
|
||||||
|
|
||||||
|
/* NID 0x0b. */
|
||||||
|
AZALIA_PIN_CFG(0x0, 0x0b, 0x0421401f),
|
||||||
|
|
||||||
|
/* NID 0x0c. */
|
||||||
|
AZALIA_PIN_CFG(0x0, 0x0c, 0x04a11020),
|
||||||
|
|
||||||
|
/* NID 0x0d. */
|
||||||
|
AZALIA_PIN_CFG(0x0, 0x0d, 0x90170110),
|
||||||
|
|
||||||
|
/* NID 0x0e. */
|
||||||
|
AZALIA_PIN_CFG(0x0, 0x0e, 0x40f000f0),
|
||||||
|
|
||||||
|
/* NID 0x0f. */
|
||||||
|
AZALIA_PIN_CFG(0x0, 0x0f, 0x40f000f0),
|
||||||
|
|
||||||
|
/* NID 0x10. */
|
||||||
|
AZALIA_PIN_CFG(0x0, 0x10, 0x40f000f0),
|
||||||
|
|
||||||
|
/* NID 0x11. */
|
||||||
|
AZALIA_PIN_CFG(0x0, 0x11, 0x90a60130),
|
||||||
|
|
||||||
|
/* NID 0x1f. */
|
||||||
|
AZALIA_PIN_CFG(0x0, 0x1f, 0x40f000f0),
|
||||||
|
|
||||||
|
/* NID 0x20. */
|
||||||
|
AZALIA_PIN_CFG(0x0, 0x20, 0x40f000f0),
|
||||||
|
0x11c11040, /* Codec Vendor / Device ID: LSI */
|
||||||
|
0x103c3066, /* Subsystem ID */
|
||||||
|
|
||||||
|
0x00000001, /* Number of 4 dword sets */
|
||||||
|
/* NID 0x01: Subsystem ID. */
|
||||||
|
AZALIA_SUBVENDOR(0x1, 0x103c3066),
|
||||||
|
};
|
||||||
|
|
||||||
|
const u32 pc_beep_verbs[0] = {};
|
||||||
|
|
||||||
|
AZALIA_ARRAY_SIZES;
|
||||||
|
|
@ -0,0 +1,28 @@
|
||||||
|
/*
|
||||||
|
* This file is part of the coreboot project.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2017 Iru Cai <mytbk920423@gmail.com>
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; version 2 of the License.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <device/device.h>
|
||||||
|
#include <drivers/intel/gma/int15.h>
|
||||||
|
|
||||||
|
static void mainboard_enable(device_t dev)
|
||||||
|
{
|
||||||
|
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
|
||||||
|
GMA_INT15_PANEL_FIT_DEFAULT,
|
||||||
|
GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
struct chip_operations mainboard_ops = {
|
||||||
|
.enable_dev = mainboard_enable,
|
||||||
|
};
|
||||||
|
|
@ -0,0 +1,82 @@
|
||||||
|
/*
|
||||||
|
* This file is part of the coreboot project.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2017 Iru Cai <mytbk920423@gmail.com>
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; version 2 of
|
||||||
|
* the License.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <arch/io.h>
|
||||||
|
#include <northbridge/intel/sandybridge/sandybridge.h>
|
||||||
|
#include <northbridge/intel/sandybridge/raminit_native.h>
|
||||||
|
#include <southbridge/intel/bd82x6x/pch.h>
|
||||||
|
#include <superio/smsc/lpc47n217/lpc47n217.h>
|
||||||
|
#include <ec/hp/kbc1126/ec.h>
|
||||||
|
|
||||||
|
#define SERIAL_DEV PNP_DEV(0x4e, LPC47N217_SP1)
|
||||||
|
|
||||||
|
void pch_enable_lpc(void)
|
||||||
|
{
|
||||||
|
/*
|
||||||
|
* CNF2 and CNF1 for Super I/O
|
||||||
|
* MC and LPC (0x60,0x64,0x62,0x66) for KBC and EC
|
||||||
|
* Enable parallel port and serial port
|
||||||
|
*/
|
||||||
|
pci_write_config16(PCH_LPC_DEV, LPC_EN,
|
||||||
|
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN |
|
||||||
|
LPT_LPC_EN | COMA_LPC_EN);
|
||||||
|
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);
|
||||||
|
/* Enable mailbox at 0x200/0x201 and PM1 at 0x220 */
|
||||||
|
pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201);
|
||||||
|
}
|
||||||
|
|
||||||
|
void rcba_config(void)
|
||||||
|
{
|
||||||
|
RCBA32(FD) = PCH_DISABLE_ALWAYS | 0x10001fe0;
|
||||||
|
}
|
||||||
|
|
||||||
|
const struct southbridge_usb_port mainboard_usb_ports[] = {
|
||||||
|
{ 1, 1, 0 },
|
||||||
|
{ 1, 0, 0 },
|
||||||
|
{ 0, 1, 1 },
|
||||||
|
{ 1, 1, 1 },
|
||||||
|
{ 1, 0, 2 },
|
||||||
|
{ 1, 0, 2 },
|
||||||
|
{ 0, 0, 3 },
|
||||||
|
{ 1, 0, 3 },
|
||||||
|
{ 1, 1, 4 },
|
||||||
|
{ 1, 1, 4 },
|
||||||
|
{ 1, 0, 5 },
|
||||||
|
{ 1, 0, 5 },
|
||||||
|
{ 1, 0, 6 },
|
||||||
|
{ 1, 0, 6 },
|
||||||
|
};
|
||||||
|
|
||||||
|
void mainboard_early_init(int s3resume)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
void mainboard_config_superio(void)
|
||||||
|
{
|
||||||
|
lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||||
|
kbc1126_enter_conf();
|
||||||
|
kbc1126_mailbox_init();
|
||||||
|
kbc1126_kbc_init();
|
||||||
|
kbc1126_ec_init();
|
||||||
|
kbc1126_pm1_init();
|
||||||
|
kbc1126_exit_conf();
|
||||||
|
}
|
||||||
|
|
||||||
|
void mainboard_get_spd(spd_raw_data *spd, bool id_only)
|
||||||
|
{
|
||||||
|
read_spd(&spd[0], 0x50, id_only);
|
||||||
|
read_spd(&spd[2], 0x52, id_only);
|
||||||
|
}
|
||||||
Loading…
Reference in New Issue