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sb/intel/bd82x6x: Fix 16-bit read/write PCI_COMMAND register 

Change-Id: I1589fd8df4ec0fcdcde283513734dfd8458df2f7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40807
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Elyes HAOUAS 2020-04-28 19:50:44 +02:00 committed by Patrick Georgi
parent c5dd57ab65
commit 729c0695e5
8 changed files with 33 additions and 52 deletions
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3
src/southbridge/intel/bd82x6x/azalia.c
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@ -281,8 +281,7 @@ static void azalia_init(struct device *dev)
} }
/* Set Bus Master */ /* Set Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND); pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);
pci_write_config8(dev, 0x3c, 0x0a); // unused? pci_write_config8(dev, 0x3c, 0x0a); // unused?

9
src/southbridge/intel/bd82x6x/early_usb_mrc.c
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@ -18,19 +18,14 @@ void enable_usb_bar(void)
{ {
pci_devfn_t usb0 = PCH_EHCI1_DEV; pci_devfn_t usb0 = PCH_EHCI1_DEV;
pci_devfn_t usb1 = PCH_EHCI2_DEV; pci_devfn_t usb1 = PCH_EHCI2_DEV;
u32 cmd;
/* USB Controller 1 */ /* USB Controller 1 */
pci_write_config32(usb0, PCI_BASE_ADDRESS_0, pci_write_config32(usb0, PCI_BASE_ADDRESS_0,
PCH_EHCI1_TEMP_BAR0); PCH_EHCI1_TEMP_BAR0);
cmd = pci_read_config32(usb0, PCI_COMMAND); pci_or_config16(usb0, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
pci_write_config32(usb0, PCI_COMMAND, cmd);
/* USB Controller 2 */ /* USB Controller 2 */
pci_write_config32(usb1, PCI_BASE_ADDRESS_0, pci_write_config32(usb1, PCI_BASE_ADDRESS_0,
PCH_EHCI2_TEMP_BAR0); PCH_EHCI2_TEMP_BAR0);
cmd = pci_read_config32(usb1, PCI_COMMAND); pci_or_config16(usb1, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
pci_write_config32(usb1, PCI_COMMAND, cmd);
} }

12
src/southbridge/intel/bd82x6x/me.c
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@ -471,6 +471,7 @@ static void intel_me7_finalize_smm(void)
{ {
struct me_hfs hfs; struct me_hfs hfs;
u32 reg32; u32 reg32;
u16 reg16;
mei_base_address = (u32 *) mei_base_address = (u32 *)
(pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf); (pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf);
@ -493,10 +494,10 @@ static void intel_me7_finalize_smm(void)
mkhi_end_of_post(); mkhi_end_of_post();
/* Make sure IO is disabled */ /* Make sure IO is disabled */
reg32 = pci_read_config32(PCH_ME_DEV, PCI_COMMAND); reg16 = pci_read_config16(PCH_ME_DEV, PCI_COMMAND);
reg32 &= ~(PCI_COMMAND_MASTER | reg16 &= ~(PCI_COMMAND_MASTER |
PCI_COMMAND_MEMORY | PCI_COMMAND_IO); PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
pci_write_config32(PCH_ME_DEV, PCI_COMMAND, reg32); pci_write_config16(PCH_ME_DEV, PCI_COMMAND, reg16);
/* Hide the PCI device */ /* Hide the PCI device */
RCBA32_OR(FD2, PCH_DISABLE_MEI1); RCBA32_OR(FD2, PCH_DISABLE_MEI1);
@ -589,7 +590,6 @@ static int intel_mei_setup(struct device *dev)
{ {
struct resource *res; struct resource *res;
struct mei_csr host; struct mei_csr host;
u32 reg32;
/* Find the MMIO base for the ME interface */ /* Find the MMIO base for the ME interface */
res = find_resource(dev, PCI_BASE_ADDRESS_0); res = find_resource(dev, PCI_BASE_ADDRESS_0);
@ -600,9 +600,7 @@ static int intel_mei_setup(struct device *dev)
mei_base_address = (u32*)(uintptr_t)res->base; mei_base_address = (u32*)(uintptr_t)res->base;
/* Ensure Memory and Bus Master bits are set */ /* Ensure Memory and Bus Master bits are set */
reg32 = pci_read_config32(dev, PCI_COMMAND); pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
pci_write_config32(dev, PCI_COMMAND, reg32);
/* Clean up status for next message */ /* Clean up status for next message */
read_host_csr(&host); read_host_csr(&host);

12
src/southbridge/intel/bd82x6x/me_8.x.c
View File

@ -435,6 +435,7 @@ void intel_me8_finalize_smm(void)
{ {
struct me_hfs hfs; struct me_hfs hfs;
u32 reg32; u32 reg32;
u16 reg16;
mei_base_address = (void *) mei_base_address = (void *)
(pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf); (pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf);
@ -457,10 +458,10 @@ void intel_me8_finalize_smm(void)
mkhi_end_of_post(); mkhi_end_of_post();
/* Make sure IO is disabled */ /* Make sure IO is disabled */
reg32 = pci_read_config32(PCH_ME_DEV, PCI_COMMAND); reg16 = pci_read_config16(PCH_ME_DEV, PCI_COMMAND);
reg32 &= ~(PCI_COMMAND_MASTER | reg16 &= ~(PCI_COMMAND_MASTER |
PCI_COMMAND_MEMORY | PCI_COMMAND_IO); PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
pci_write_config32(PCH_ME_DEV, PCI_COMMAND, reg32); pci_write_config16(PCH_ME_DEV, PCI_COMMAND, reg16);
/* Hide the PCI device */ /* Hide the PCI device */
RCBA32_OR(FD2, PCH_DISABLE_MEI1); RCBA32_OR(FD2, PCH_DISABLE_MEI1);
@ -545,7 +546,6 @@ static int intel_mei_setup(struct device *dev)
{ {
struct resource *res; struct resource *res;
struct mei_csr host; struct mei_csr host;
u32 reg32;
/* Find the MMIO base for the ME interface */ /* Find the MMIO base for the ME interface */
res = find_resource(dev, PCI_BASE_ADDRESS_0); res = find_resource(dev, PCI_BASE_ADDRESS_0);
@ -556,9 +556,7 @@ static int intel_mei_setup(struct device *dev)
mei_base_address = (u32 *)(uintptr_t)res->base; mei_base_address = (u32 *)(uintptr_t)res->base;
/* Ensure Memory and Bus Master bits are set */ /* Ensure Memory and Bus Master bits are set */
reg32 = pci_read_config32(dev, PCI_COMMAND); pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
pci_write_config32(dev, PCI_COMMAND, reg32);
/* Clean up status for next message */ /* Clean up status for next message */
read_host_csr(&host); read_host_csr(&host);

24
src/southbridge/intel/bd82x6x/pch.c
View File

@ -301,7 +301,7 @@ static void pch_pcie_devicetree_update(
static void pch_pcie_enable(struct device *dev) static void pch_pcie_enable(struct device *dev)
{ {
struct southbridge_intel_bd82x6x_config *config = dev->chip_info; struct southbridge_intel_bd82x6x_config *config = dev->chip_info;
u32 reg32; u16 reg16;
if (!config) if (!config)
return; return;
@ -358,10 +358,10 @@ static void pch_pcie_enable(struct device *dev)
} }
/* Ensure memory, io, and bus master are all disabled */ /* Ensure memory, io, and bus master are all disabled */
reg32 = pci_read_config32(dev, PCI_COMMAND); reg16 = pci_read_config16(dev, PCI_COMMAND);
reg32 &= ~(PCI_COMMAND_MASTER | reg16 &= ~(PCI_COMMAND_MASTER |
PCI_COMMAND_MEMORY | PCI_COMMAND_IO); PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
pci_write_config32(dev, PCI_COMMAND, reg32); pci_write_config16(dev, PCI_COMMAND, reg16);
/* Do not claim downstream transactions for PCIe ports */ /* Do not claim downstream transactions for PCIe ports */
new_rpfn |= RPFN_HIDE(PCI_FUNC(dev->path.pci.devfn)); new_rpfn |= RPFN_HIDE(PCI_FUNC(dev->path.pci.devfn));
@ -388,9 +388,7 @@ static void pch_pcie_enable(struct device *dev)
} }
/* Enable SERR */ /* Enable SERR */
reg32 = pci_read_config32(dev, PCI_COMMAND); pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR);
reg32 |= PCI_COMMAND_SERR;
pci_write_config32(dev, PCI_COMMAND, reg32);
} }
/* /*
@ -410,7 +408,7 @@ static void pch_pcie_enable(struct device *dev)
void pch_enable(struct device *dev) void pch_enable(struct device *dev)
{ {
u32 reg32; u16 reg16;
/* PCH PCIe Root Ports get special handling */ /* PCH PCIe Root Ports get special handling */
if (PCI_SLOT(dev->path.pci.devfn) == PCH_PCIE_DEV_SLOT) if (PCI_SLOT(dev->path.pci.devfn) == PCH_PCIE_DEV_SLOT)
@ -420,18 +418,16 @@ void pch_enable(struct device *dev)
printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev));
/* Ensure memory, io, and bus master are all disabled */ /* Ensure memory, io, and bus master are all disabled */
reg32 = pci_read_config32(dev, PCI_COMMAND); reg16 = pci_read_config16(dev, PCI_COMMAND);
reg32 &= ~(PCI_COMMAND_MASTER | reg16 &= ~(PCI_COMMAND_MASTER |
PCI_COMMAND_MEMORY | PCI_COMMAND_IO); PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
pci_write_config32(dev, PCI_COMMAND, reg32); pci_write_config16(dev, PCI_COMMAND, reg16);
/* Hide this device if possible */ /* Hide this device if possible */
pch_hide_devfn(dev->path.pci.devfn); pch_hide_devfn(dev->path.pci.devfn);
} else { } else {
/* Enable SERR */ /* Enable SERR */
reg32 = pci_read_config32(dev, PCI_COMMAND); pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR);
reg32 |= PCI_COMMAND_SERR;
pci_write_config32(dev, PCI_COMMAND, reg32);
} }
} }

6
src/southbridge/intel/bd82x6x/pcie.c
View File

@ -205,15 +205,12 @@ static void pch_pcie_pm_late(struct device *dev)
static void pci_init(struct device *dev) static void pci_init(struct device *dev)
{ {
u16 reg16; u16 reg16;
u32 reg32;
struct southbridge_intel_bd82x6x_config *config = dev->chip_info; struct southbridge_intel_bd82x6x_config *config = dev->chip_info;
printk(BIOS_DEBUG, "Initializing PCH PCIe bridge.\n"); printk(BIOS_DEBUG, "Initializing PCH PCIe bridge.\n");
/* Enable Bus Master */ /* Enable Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND); pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
reg32 |= PCI_COMMAND_MASTER;
pci_write_config32(dev, PCI_COMMAND, reg32);
/* Set Cache Line Size to 0x10 */ /* Set Cache Line Size to 0x10 */
// This has no effect but the OS might expect it // This has no effect but the OS might expect it
@ -225,6 +222,7 @@ static void pci_init(struct device *dev)
pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16); pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16);
#ifdef EVEN_MORE_DEBUG #ifdef EVEN_MORE_DEBUG
u32 reg32;
reg32 = pci_read_config32(dev, 0x20); reg32 = pci_read_config32(dev, 0x20);
printk(BIOS_SPEW, " MBL = 0x%08x\n", reg32); printk(BIOS_SPEW, " MBL = 0x%08x\n", reg32);
reg32 = pci_read_config32(dev, 0x24); reg32 = pci_read_config32(dev, 0x24);

13
src/southbridge/intel/bd82x6x/smihandler.c
View File

@ -93,7 +93,7 @@ void southbridge_gate_memory_reset(void)
static void xhci_sleep(u8 slp_typ) static void xhci_sleep(u8 slp_typ)
{ {
u32 reg32, xhci_bar; u32 xhci_bar;
u16 reg16; u16 reg16;
switch (slp_typ) { switch (slp_typ) {
@ -103,9 +103,8 @@ static void xhci_sleep(u8 slp_typ)
reg16 &= ~0x03UL; reg16 &= ~0x03UL;
pci_write_config32(PCH_XHCI_DEV, 0x74, reg16); pci_write_config32(PCH_XHCI_DEV, 0x74, reg16);
reg32 = pci_read_config32(PCH_XHCI_DEV, PCI_COMMAND); pci_or_config16(PCH_XHCI_DEV, PCI_COMMAND, PCI_COMMAND_MASTER |
reg32 |= (PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); PCI_COMMAND_MEMORY);
pci_write_config32(PCH_XHCI_DEV, PCI_COMMAND, reg32);
xhci_bar = pci_read_config32(PCH_XHCI_DEV, xhci_bar = pci_read_config32(PCH_XHCI_DEV,
PCI_BASE_ADDRESS_0) & ~0xFUL; PCI_BASE_ADDRESS_0) & ~0xFUL;
@ -119,9 +118,9 @@ static void xhci_sleep(u8 slp_typ)
if ((xhci_bar + 0x4F0) & 1) if ((xhci_bar + 0x4F0) & 1)
pch_iobp_update(0xEC000382, ~0UL, (3 << 2)); pch_iobp_update(0xEC000382, ~0UL, (3 << 2));
reg32 = pci_read_config32(PCH_XHCI_DEV, PCI_COMMAND); reg16 = pci_read_config16(PCH_XHCI_DEV, PCI_COMMAND);
reg32 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
pci_write_config32(PCH_XHCI_DEV, PCI_COMMAND, reg32); pci_write_config16(PCH_XHCI_DEV, PCI_COMMAND, reg16);
reg16 = pci_read_config16(PCH_XHCI_DEV, 0x74); reg16 = pci_read_config16(PCH_XHCI_DEV, 0x74);
reg16 |= 0x03; reg16 |= 0x03;

6
src/southbridge/intel/bd82x6x/usb_ehci.c
View File

@ -30,10 +30,8 @@ static void usb_ehci_init(struct device *dev)
pci_write_config32(dev, 0xfc, 0x205b1708); pci_write_config32(dev, 0xfc, 0x205b1708);
#endif #endif
reg32 = pci_read_config32(dev, PCI_COMMAND); pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
reg32 |= PCI_COMMAND_MASTER; //pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR);
//reg32 |= PCI_COMMAND_SERR;
pci_write_config32(dev, PCI_COMMAND, reg32);
/* For others, done in MRC. */ /* For others, done in MRC. */
#if CONFIG(USE_NATIVE_RAMINIT) #if CONFIG(USE_NATIVE_RAMINIT)