From 72c83a8e231cd4fbc5b9fcec53e4b7b26ce4f144 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Mon, 7 Dec 2015 12:22:23 -0600 Subject: [PATCH] sb/amd/sr5650: Allow resource allocator to assign bus numbers At some point in the past disconnected PCIe bridges were completely disabled to work around a hang on bridge probe. This hang was resolved at some point, and the disconnected PCIe bridges should be enabled to receive a bus number per the RPR. This resolves a slew of warnings in the Linux boot log regarding invalid bridge configurations for disconnected bridge devices. Change-Id: Ic26e2d62ec5ddb9f22275c2afec7d560326263c7 Signed-off-by: Timothy Pearson Reviewed-on: https://review.coreboot.org/12673 Tested-by: Raptor Engineering Automated Test Stand Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Paul Menzel --- src/southbridge/amd/sr5650/pcie.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/southbridge/amd/sr5650/pcie.c b/src/southbridge/amd/sr5650/pcie.c index 762e632c2a..e198b87324 100644 --- a/src/southbridge/amd/sr5650/pcie.c +++ b/src/southbridge/amd/sr5650/pcie.c @@ -768,11 +768,12 @@ void sr5650_gpp_sb_init(device_t nb_dev, device_t dev, u32 port) if (res) { AtiPcieCfg.PortDetect |= 1 << port; } else { - /* If the training failed the disable the bridge to prevent subsequent - * lockup on bridge configuration register read during the PCI bus scan + /* Even though nothing is attached to this port + * the port needs to be "enabled" to obtain + * a bus number from the PCI resource allocator */ training_ok = 0; - dev->enabled = 0; + dev->enabled = 1; } } }