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mb/google/guybrush: Add PCIe Reset GPIO18 to PCIE WWAN DXIO Descriptor 

WWAN_AUX_RST_L is asserted during S0i3 entry. But it needs to be
de-asserted before PCIe link training during S0i3 resume. Otherwise the
concerned gpp_bridge_2 PCIe device is not enumerated on Soi3 resume.
This change feeds in the WWAN_AUX_RST_L GPIO in the DXIO descriptor so
that SMU de-asserts this reset on S0i3 resume.

BUG=b:199780346
TEST=Build and boot to OS in Guybrush. Perform suspend/resume cycles for
500 iterations. Ensure that the PCIe devices enumerate fine.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I588c490bf3f8a7beffefc3bfd8ca5167fcbcb9a5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58459
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This commit is contained in:
Karthikeyan Ramasubramanian 2021-10-19 15:38:36 -06:00 committed by Raul Rangel
parent 0bf9afed7f
commit 72cc0467d7
1 changed files with 3 additions and 0 deletions
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3
src/mainboard/google/guybrush/port_descriptors.c
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@ -135,6 +135,9 @@ void mainboard_get_dxio_ddi_descriptors(
if (is_dev_enabled(DEV_PTR(gpp_bridge_2))) if (is_dev_enabled(DEV_PTR(gpp_bridge_2)))
guybrush_czn_dxio_descriptors[WWAN_NVME].engine_type = PCIE_ENGINE; guybrush_czn_dxio_descriptors[WWAN_NVME].engine_type = PCIE_ENGINE;
if (variant_has_pcie_wwan())
guybrush_czn_dxio_descriptors[WWAN_NVME].gpio_group_id = GPIO_18;
*dxio_descs = guybrush_czn_dxio_descriptors; *dxio_descs = guybrush_czn_dxio_descriptors;
*dxio_num = ARRAY_SIZE(guybrush_czn_dxio_descriptors); *dxio_num = ARRAY_SIZE(guybrush_czn_dxio_descriptors);