diff --git a/src/mainboard/amd/bimini_fam10/Kconfig b/src/mainboard/amd/bimini_fam10/Kconfig
index 3a184d8f09..d39da7bfdb 100644
--- a/src/mainboard/amd/bimini_fam10/Kconfig
+++ b/src/mainboard/amd/bimini_fam10/Kconfig
@@ -16,18 +16,17 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_BUS_CONFIG
 	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE
-	select HAVE_MP_TABLE
+	select GENERATE_MP_TABLE
 	select HAVE_MAINBOARD_RESOURCES
 	select HAVE_HARD_RESET
 	select SB_HT_CHAIN_UNITID_OFFSET_ONLY
 	select LIFT_BSP_APIC_ID
 	select SERIAL_CPU_INIT
 	select AMDMCT
-	select HAVE_ACPI_TABLES
+	select GENERATE_ACPI_TABLES
 	select BOARD_ROMSIZE_KB_2048
 	select RAMINIT_SYSINFO
 	select ENABLE_APIC_EXT_ID
-	select TINY_BOOTBLOCK
 	select GFXUMA
 	select HAVE_DEBUG_CAR
 	select SET_FIDVID
diff --git a/src/southbridge/amd/sb800/bootblock.c b/src/southbridge/amd/sb800/bootblock.c
index 7a67a946d8..82d80f08a8 100644
--- a/src/southbridge/amd/sb800/bootblock.c
+++ b/src/southbridge/amd/sb800/bootblock.c
@@ -36,8 +36,7 @@ static void sb800_enable_rom(void)
 	u8 reg8;
 	device_t dev;
 
-	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_ATI,
-				       PCI_DEVICE_ID_ATI_SB800_LPC), 0);
+	dev = PCI_DEV(0, 0x14, 3);
 
 	/* Decode variable LPC ROM address ranges 1 and 2. */
 	reg8 = pci_read_config8(dev, 0x48);
diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c
index 248b1f5082..4672ada216 100644
--- a/src/southbridge/amd/sb800/early_setup.c
+++ b/src/southbridge/amd/sb800/early_setup.c
@@ -65,6 +65,8 @@ static void sb800_acpi_init(void) {
 					* the contents of the PM registers at
 					* index 60-6B to decode ACPI I/O address.
 					* AcpiSmiEn & SmiCmdEn*/
+	/* RTC_En_En, TMR_En_En, GBL_EN_EN */
+	outl(0x1, ACPI_PM1_CNT_BLK);		  /* set SCI_EN */
 }
 
 /* RPR 2.28 Get SB ASIC Revision.*/
@@ -568,11 +570,11 @@ static void sb800_pci_cfg(void)
 	byte |= (1 << 3);
 	pci_write_config8(dev, 0x41, byte);
 
-	/* Set to 1 to reset USB on the software (such as IO-64 or IO-CF9 cycles)
+	/* rpr 7.4. Set to 1 to reset USB on the software (such as IO-64 or IO-CF9 cycles)
 	 * generated PCIRST#. */
-	byte = pmio_read(0x65);
-	byte |= (1 << 4);
-	pmio_write(0x65, byte);
+	byte = pmio_read(0xF0);
+	byte |= (1 << 2);
+	pmio_write(0xF0, byte);
 
 	/* IDE Device, BDF:0-20-1 */
 	dev = PCI_DEV(0, 0x14, 1);//pci_locate_device(PCI_ID(0x1002, 0x439C), 0);
diff --git a/src/southbridge/amd/sb800/fadt.c b/src/southbridge/amd/sb800/fadt.c
index 6eb5c0a737..fece94398a 100644
--- a/src/southbridge/amd/sb800/fadt.c
+++ b/src/southbridge/amd/sb800/fadt.c
@@ -38,7 +38,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	memset((void *)fadt, 0, sizeof(acpi_fadt_t));
 	memcpy(header->signature, "FACP", 4);
 	header->length = 244;
-	header->revision = 3;
+	header->revision = 1;	/* TODO: 3 will make linux hang. */
 	memcpy(header->oem_id, OEM_ID, 6);
 	memcpy(header->oem_table_id, "COREBOOT", 8);
 	memcpy(header->asl_compiler_id, ASLC, 4);