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mb/amd/(birman|mayan): Update chromeos.fmd files 

Because the EFS is now fixed at 0xff020000, the ChromeOS RO region needs
to be moved to the bottom of the ROM area to cover that space.

The RO Region 6MiB, but you can't actually set 6MiB as RO - it's either
4 or 8MiB, so that's adjusted.  To leave some room for the RW_LEGACY
region, the two RW regions are adjusted to 3MiB each, which should be
plenty.

The GBB region had to be moved from the front of the WP_RO region to the
end to avoid conflicting with the EFS, which needs to be inside the
coreboot cbfs area.

Also get rid of AMD_FWM_POSITION_INDEX.  The FWM position is no longer
needed.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I683155ec0f4e6a62d862b9e2fa76af45f4cd5493
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Martin Roth 2023-01-09 21:38:09 -07:00 committed by Felix Held
parent 0c45df8ddb
commit 72f0501881
4 changed files with 26 additions and 38 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/mainboard/amd/birman/Kconfig
View File

@ -30,12 +30,6 @@ config DEVICETREE
default "devicetree_glinda.cb" if BOARD_AMD_BIRMAN_GLINDA
default "devicetree_phoenix.cb"
config AMD_FWM_POSITION_INDEX
int
default 3 if CHROMEOS
help
TODO: might need to be adapted for better placement of files in cbfs
config BIRMAN_HAVE_MCHP_FW
bool "Have Microchip EC firmware?"
default n

24
src/mainboard/amd/birman/chromeos.fmd
View File

@ -1,13 +1,21 @@
FLASH@0xFF000000 16M {
SI_BIOS {
WP_RO 8M {
EC 4K
RW_MRC_CACHE(PRESERVE) 120K
RW_SECTION_A 4M {
RO_VPD(PRESERVE) 16K
RO_SECTION {
FMAP 2K
RO_FRID 64
COREBOOT(CBFS)
GBB 448K
}
}
RW_SECTION_A 3M {
VBLOCK_A 8K
FW_MAIN_A(CBFS)
RW_FWID_A 256
}
RW_SECTION_B 4M {
RW_SECTION_B 3M {
VBLOCK_B 8K
FW_MAIN_B(CBFS)
RW_FWID_B 256
@ -21,14 +29,6 @@ FLASH@0xFF000000 16M {
RW_NVRAM(PRESERVE) 20K
SMMSTORE(PRESERVE) 64K
RW_LEGACY(CBFS)
WP_RO@10M 6M {
RO_VPD(PRESERVE) 16K
RO_SECTION {
FMAP 2K
RO_FRID 64
GBB@4K 448K
COREBOOT(CBFS)
}
}
RW_MRC_CACHE(PRESERVE) 120K
}
}

6
src/mainboard/amd/mayan/Kconfig
View File

@ -28,12 +28,6 @@ config MAINBOARD_PART_NUMBER
config DEVICETREE
default "devicetree_phoenix.cb"
config AMD_FWM_POSITION_INDEX
int
default 3 if CHROMEOS
help
TODO: might need to be adapted for better placement of files in cbfs
config MAYAN_HAVE_MCHP_FW
bool "Have Microchip EC firmware?"
default n

24
src/mainboard/amd/mayan/chromeos.fmd
View File

@ -1,13 +1,21 @@
FLASH@0xFF000000 16M {
SI_BIOS {
WP_RO 8M {
EC 4K
RW_MRC_CACHE(PRESERVE) 120K
RW_SECTION_A 4M {
RO_VPD(PRESERVE) 16K
RO_SECTION {
FMAP 2K
RO_FRID 64
COREBOOT(CBFS)
GBB 448K
}
}
RW_SECTION_A 3M {
VBLOCK_A 8K
FW_MAIN_A(CBFS)
RW_FWID_A 256
}
RW_SECTION_B 4M {
RW_SECTION_B 3M {
VBLOCK_B 8K
FW_MAIN_B(CBFS)
RW_FWID_B 256
@ -21,14 +29,6 @@ FLASH@0xFF000000 16M {
RW_NVRAM(PRESERVE) 20K
SMMSTORE(PRESERVE) 64K
RW_LEGACY(CBFS)
WP_RO@10M 6M {
RO_VPD(PRESERVE) 16K
RO_SECTION {
FMAP 2K
RO_FRID 64
GBB@4K 448K
COREBOOT(CBFS)
}
}
RW_MRC_CACHE(PRESERVE) 120K
}
}