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sb/intel/lynxpoint/pcie: Fix clock gating routine 

The use of `1 < 5` as a bit mask was obviously a typo. Correct it as
`1 << 5` to match what Intel doc #493816 (Lynx Point PCH BWG) states.

Change-Id: I85734a68a42ec65b124d68514039a1dda7946adc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45713
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2020-09-25 00:23:20 +02:00 committed by Michael Niewöhner
parent d3318cfe49
commit 72f4dda6b7
1 changed files with 1 additions and 2 deletions
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3
src/southbridge/intel/lynxpoint/pcie.c
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@ -283,8 +283,7 @@ static void pcie_enable_clock_gating(void)
/* Update PECR1 register. */
pci_or_config8(dev, 0xe8, 1);
/* FIXME: Are we supposed to update this register with a constant boolean? */
pci_update_config8(dev, 0x324, ~(1 << 5), (1 < 5));
pci_or_config8(dev, 0x324, 1 << 5);
/* Per-Port CLKREQ# handling. */
if (is_lp && gpio_is_native(18 + rp - 1))