superio/ite: Add IT8786E-I
Based on IT8786E-I V0.4.1 datasheet with following remark: "Please note that the IT8786E-I V0.4.1 is applicable only to the D version." Signed-off-by: Kyösti Mälkki <kyosti.malkki@3mdeb.com> Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I7317da6a72db64f95f9a790ef96ed7a5f93b3aea Reviewed-on: https://review.coreboot.org/c/coreboot/+/30335 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Kyösti Mälkki
Patrick Georgi
parent
dcfff3739b
commit
72f6fbb1bc
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@ -2,6 +2,7 @@
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2009 Ronald G. Minnich
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## Copyright (C) 2018 Libretrend LDA
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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@ -31,3 +32,4 @@ subdirs-y += it8721f
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subdirs-y += it8728f
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subdirs-y += it8772f
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subdirs-y += it8783ef
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subdirs-y += it8786e
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@ -0,0 +1,23 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2016 secunet Security Networks AG
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## Copyright (C) 2018 Libretrend LDA
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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config SUPERIO_ITE_IT8786E
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bool
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select SUPERIO_ITE_COMMON_PRE_RAM
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select SUPERIO_ITE_ENV_CTRL
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select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2
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select SUPERIO_ITE_ENV_CTRL_8BIT_PWM
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select SUPERIO_ITE_ENV_CTRL_7BIT_SLOPE_REG
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@ -0,0 +1,18 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2016 secunet Security Networks AG
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## Copyright (C) 2018 Libretrend LDA
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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ramstage-$(CONFIG_SUPERIO_ITE_IT8786E) += superio.c
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@ -0,0 +1,171 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Christoph Grenz <christophg+cb@grenz-bonn.de>
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* Copyright (C) 2013, 2016 secunet Security Networks AG
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/*
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* Include this file into a mainboard's DSDT _SB device tree and it will
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* expose the IT8786E SuperIO and some of its functionality.
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*
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* It allows the change of IO ports, IRQs and DMA settings on logical
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* devices, disabling and reenabling logical devices.
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*
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* LDN State
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* 0x1 UARTA Implemented, untested
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* 0x2 UARTB Implemented, untested
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* 0x3 PP Not implemented
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* 0x4 EC Not implemented
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* 0x5 KBC Implemented, untested
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* 0x6 MOUSE Implemented, untested
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* 0x7 GPIO Not implemented
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* 0x8 UARTC Implemented, untested
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* 0x9 UARTD Implemented, untested
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* 0xa UARTE Not implemented
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* 0xb UARTF Not implemented
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* 0xc CIR Not implemented
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*
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* Controllable through preprocessor defines:
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* SUPERIO_DEV Device identifier for this SIO (e.g. SIO0)
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* SUPERIO_PNP_BASE I/O address of the first PnP configuration register
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* IT8786E_SHOW_UARTA If defined, UARTA will be exposed.
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* IT8786E_SHOW_UARTB If defined, UARTB will be exposed.
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* IT8786E_SHOW_UARTC If defined, UARTC will be exposed.
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* IT8786E_SHOW_UARTD If defined, UARTD will be exposed.
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* IT8786E_SHOW_KBC If defined, the KBC will be exposed.
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* IT8786E_SHOW_PS2M If defined, PS/2 mouse support will be exposed.
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*/
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#undef SUPERIO_CHIP_NAME
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#define SUPERIO_CHIP_NAME IT8786E
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#include <superio/acpi/pnp.asl>
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#undef PNP_DEFAULT_PSC
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#define PNP_DEFAULT_PSC Return (0) /* no power management */
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#define CONFIGURE_CONTROL CCTL
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Device (SUPERIO_DEV) {
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Name (_HID, EisaId("PNP0A05"))
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Name (_STR, Unicode("ITE IT8786E Super I/O"))
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Name (_UID, SUPERIO_UID(SUPERIO_DEV,))
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/* Mutex for accesses to the configuration ports */
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Mutex (CRMX, 1)
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/* SuperIO configuration ports */
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OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 0x02)
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Field (CREG, ByteAcc, NoLock, Preserve)
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{
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PNP_ADDR_REG, 8,
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PNP_DATA_REG, 8
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}
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IndexField (ADDR, DATA, ByteAcc, NoLock, Preserve)
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{
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Offset (0x02),
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CONFIGURE_CONTROL, 8, /* Global configure control */
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Offset (0x07),
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PNP_LOGICAL_DEVICE, 8, /* Logical device selector */
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Offset (0x30),
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PNP_DEVICE_ACTIVE, 1, /* Logical device activation */
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Offset (0x60),
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PNP_IO0_HIGH_BYTE, 8, /* First I/O port base - high byte */
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PNP_IO0_LOW_BYTE, 8, /* First I/O port base - low byte */
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Offset (0x62),
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PNP_IO1_HIGH_BYTE, 8, /* Second I/O port base - high byte */
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PNP_IO1_LOW_BYTE, 8, /* Second I/O port base - low byte */
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Offset (0x70),
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PNP_IRQ0, 8, /* First IRQ */
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}
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Method (_CRS)
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{
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/* Announce the used i/o ports to the OS */
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Return (ResourceTemplate () {
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IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE,
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0x01, 0x02)
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})
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}
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#undef PNP_ENTER_MAGIC_1ST
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#undef PNP_ENTER_MAGIC_2ND
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#undef PNP_ENTER_MAGIC_3RD
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#undef PNP_ENTER_MAGIC_4TH
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#undef PNP_EXIT_MAGIC_1ST
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#define PNP_ENTER_MAGIC_1ST 0x87
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#define PNP_ENTER_MAGIC_2ND 0x01
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#define PNP_ENTER_MAGIC_3RD 0x55
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#if SUPERIO_PNP_BASE == 0x2e
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#define PNP_ENTER_MAGIC_4TH 0x55
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#else
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#define PNP_ENTER_MAGIC_4TH 0xaa
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#endif
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#define PNP_EXIT_SPECIAL_REG CONFIGURE_CONTROL
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#define PNP_EXIT_SPECIAL_VAL 0x02
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#include <superio/acpi/pnp_config.asl>
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#ifdef IT8786E_SHOW_UARTA
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#undef SUPERIO_UART_LDN
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#undef SUPERIO_UART_DDN
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#undef SUPERIO_UART_PM_REG
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#undef SUPERIO_UART_PM_VAL
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#undef SUPERIO_UART_PM_LDN
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#define SUPERIO_UART_LDN 1
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#include <superio/acpi/pnp_uart.asl>
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#endif
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#ifdef IT8786E_SHOW_UARTB
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#undef SUPERIO_UART_LDN
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#undef SUPERIO_UART_DDN
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#undef SUPERIO_UART_PM_REG
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#undef SUPERIO_UART_PM_VAL
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#undef SUPERIO_UART_PM_LDN
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#define SUPERIO_UART_LDN 2
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#include <superio/acpi/pnp_uart.asl>
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#endif
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#ifdef IT8786E_SHOW_KBC
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#undef SUPERIO_KBC_LDN
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#undef SUPERIO_KBC_PS2M
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#undef SUPERIO_KBC_PS2LDN
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#define SUPERIO_KBC_LDN 5
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#ifdef IT8786E_SHOW_PS2M
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#define SUPERIO_KBC_PS2LDN 6
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#endif
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#include <superio/acpi/pnp_kbc.asl>
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#endif
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#ifdef IT8786E_SHOW_UARTC
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#undef SUPERIO_UART_LDN
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#undef SUPERIO_UART_DDN
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#undef SUPERIO_UART_PM_REG
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#undef SUPERIO_UART_PM_VAL
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#undef SUPERIO_UART_PM_LDN
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#define SUPERIO_UART_LDN 8
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#include <superio/acpi/pnp_uart.asl>
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#endif
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#ifdef IT8786E_SHOW_UARTD
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#undef SUPERIO_UART_LDN
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#undef SUPERIO_UART_DDN
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#undef SUPERIO_UART_PM_REG
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#undef SUPERIO_UART_PM_VAL
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#undef SUPERIO_UART_PM_LDN
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#define SUPERIO_UART_LDN 9
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#include <superio/acpi/pnp_uart.asl>
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#endif
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}
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@ -0,0 +1,27 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2016 secunet Security Networks AG
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* Copyright (C) 2019 Libretrend LDA
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef SUPERIO_ITE_IT8786E_CHIP_H
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#define SUPERIO_ITE_IT8786E_CHIP_H
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#include <superio/ite/common/env_ctrl_chip.h>
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struct superio_ite_it8786e_config {
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struct ite_ec_config ec;
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};
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#endif /* SUPERIO_ITE_IT8786E_CHIP_H */
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@ -0,0 +1,36 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2016 secunet Security Networks AG
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* Copyright (C) 2019 Libretrend LDA
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef SUPERIO_ITE_IT8786E_H
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#define SUPERIO_ITE_IT8786E_H
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#define IT8786E_SP1 0x01 /* COM1 */
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#define IT8786E_SP2 0x02 /* COM2 */
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#define IT8786E_PP 0x03 /* Printer port */
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#define IT8786E_EC 0x04 /* Environment controller */
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#define IT8786E_KBCK 0x05 /* Keyboard */
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#define IT8786E_KBCM 0x06 /* Mouse */
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#define IT8786E_GPIO 0x07 /* GPIO */
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#define IT8786E_SP3 0x08 /* COM3 */
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#define IT8786E_SP4 0x09 /* COM4 */
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#define IT8786E_CIR 0x0a /* Consumer IR */
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#define IT8786E_SP5 0x0b /* COM5 */
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#define IT8786E_SP6 0x0c /* COM6 */
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#include <stdint.h>
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#endif /* SUPERIO_ITE_IT8786E_H */
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@ -0,0 +1,118 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2016 secunet Security Networks AG
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* Copyright (C) 2019 Libretrend LDA
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <device/device.h>
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#include <device/pnp.h>
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#include <pc80/keyboard.h>
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#include <superio/conf_mode.h>
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#include <superio/ite/common/env_ctrl.h>
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#include "it8786e.h"
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#include "chip.h"
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static void it8786e_init(struct device *const dev)
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{
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const struct superio_ite_it8786e_config *conf;
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const struct resource *res;
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if (!dev->enabled)
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return;
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switch (dev->path.pnp.device) {
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case IT8786E_EC:
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conf = dev->chip_info;
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res = find_resource(dev, PNP_IDX_IO0);
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if (!conf || !res)
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break;
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ite_ec_init(res->base, &conf->ec);
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break;
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case IT8786E_KBCK:
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pc_keyboard_init(NO_AUX_DEVICE);
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break;
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default:
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break;
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}
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}
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static struct device_operations ops = {
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.read_resources = pnp_read_resources,
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.set_resources = pnp_set_resources,
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.enable_resources = pnp_enable_resources,
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.enable = pnp_alt_enable,
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.init = it8786e_init,
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.ops_pnp_mode = &pnp_conf_mode_870155_aa,
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};
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static struct pnp_info pnp_dev_info[] = {
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/* Serial Port 1 */
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{ NULL, IT8786E_SP1, PNP_IO0 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1 |
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PNP_MSC2,
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0x0ff8, },
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/* Serial Port 2 */
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{ NULL, IT8786E_SP2, PNP_IO0 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1 |
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PNP_MSC2,
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0x0ff8, },
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/* Printer Port */
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{ NULL, IT8786E_PP, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_DRQ0 |
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PNP_MSC0,
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0x0ff8, 0x0ffc, },
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/* Environmental Controller */
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{ NULL, IT8786E_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0 |
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PNP_MSC1 | PNP_MSC2 | PNP_MSC3 | PNP_MSC4 |
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PNP_MSC5 | PNP_MSC6 | PNP_MSCA | PNP_MSCB |
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PNP_MSCC,
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0x0ff8, 0x0ffc, },
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/* KBC Keyboard */
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{ NULL, IT8786E_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0,
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0x0fff, 0x0fff, },
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/* KBC Mouse */
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{ NULL, IT8786E_KBCM, PNP_IRQ0 | PNP_MSC0, },
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/* GPIO */
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{ NULL, IT8786E_GPIO, PNP_IO0 | PNP_IO1 | PNP_IRQ0 |
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PNP_MSC0 | PNP_MSC1 | PNP_MSC2 | PNP_MSC3 |
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PNP_MSC4 | PNP_MSC5 | PNP_MSC6 | PNP_MSC7 |
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PNP_MSC8 | PNP_MSC9 | PNP_MSCA | PNP_MSCB,
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0x0ffc, 0x0fff, },
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/* Serial Port 3 */
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{ NULL, IT8786E_SP3, PNP_IO0 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1 |
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PNP_MSC2,
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0x0ff8, },
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/* Serial Port 4 */
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{ NULL, IT8786E_SP4, PNP_IO0 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1 |
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PNP_MSC2,
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0x0ff8, },
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/* Consumer Infrared */
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{ NULL, IT8786E_CIR, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0x0ff8, },
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/* Serial Port 5 */
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{ NULL, IT8786E_SP5, PNP_IO0 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1 |
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PNP_MSC2,
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0x0ff8, },
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/* Serial Port 6 */
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{ NULL, IT8786E_SP6, PNP_IO0 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1 |
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PNP_MSC2,
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0x0ff8, },
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};
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static void enable_dev(struct device *dev)
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{
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pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
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}
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struct chip_operations superio_ite_it8786e_ops = {
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CHIP_NAME("ITE IT8786E Super I/O")
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.enable_dev = enable_dev,
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};
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