soc/intel/common: Order the different types of cores based on APIC IDs

Currently coreboot presents the BSP core first, then efficient cores and
Performance cores as indicated below:

```
/sys/devices/system/cpu/cpu0/topology/thread_siblings_list:0-1
/sys/devices/system/cpu/cpu4/topology/thread_siblings_list:4
/sys/devices/system/cpu/cpu5/topology/thread_siblings_list:5
/sys/devices/system/cpu/cpu6/topology/thread_siblings_list:6
/sys/devices/system/cpu/cpu7/topology/thread_siblings_list:7
/sys/devices/system/cpu/cpu1/topology/thread_siblings_list:0-1
/sys/devices/system/cpu/cpu2/topology/thread_siblings_list:2-3
/sys/devices/system/cpu/cpu3/topology/thread_siblings_list:2-3

```
Existing code presents mix of different cores to OS and causes CPU load
balancing and power/performance impact. So, the patch fixes this
disorder by ordering the Performance cores first, compute die efficient
cores next, and finally SOC efficient cores if they are present. This
is done to run the media applications in a power efficient manner,
please refer the ChromeOS patches for details:
https://chromium-review.googlesource.com/c/chromiumos/platform2/+/3963893

BUG=b:262886449
TEST=Verified the code on Rex system

After the fix:

```
/sys/devices/system/cpu/cpu0/topology/thread_siblings_list:0-1
/sys/devices/system/cpu/cpu1/topology/thread_siblings_list:0-1
/sys/devices/system/cpu/cpu2/topology/thread_siblings_list:2-3
/sys/devices/system/cpu/cpu3/topology/thread_siblings_list:2-3
/sys/devices/system/cpu/cpu4/topology/thread_siblings_list:4
/sys/devices/system/cpu/cpu5/topology/thread_siblings_list:5
/sys/devices/system/cpu/cpu6/topology/thread_siblings_list:6
/sys/devices/system/cpu/cpu7/topology/thread_siblings_list:7
```

Change-Id: I21487a5eb0439ea0cb5976787d1769ee94777469
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>

src/soc/intel/common/block/acpi/acpi.c

@@ -87,7 +87,11 @@ unsigned long acpi_fill_madt(unsigned long current)
 	size_t ioapic_entries;
 
 	/* Local APICs */
-	current = acpi_create_madt_lapics_with_nmis(current);
+
+	if (CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID))
+		current = acpi_create_madt_lapics_with_nmis_hybrid(current);
+	else
+		current = acpi_create_madt_lapics_with_nmis(current);
 
 	/* IOAPIC */
 	ioapic_entries = soc_get_ioapic_info(&ioapic_table);

src/soc/intel/common/block/acpi/cpu_hybrid.c

@@ -77,6 +77,40 @@ static void acpi_set_hybrid_cpu_apicid_order(void *unused)
 	cpu_apic_info.perf_cpu_cnt = perf_core_cnt;
 }
 
+static unsigned long acpi_create_madt_lapics_hybrid(unsigned long current)
+{
+	size_t index;
+
+	for (index = 0; index < cpu_apic_info.total_cpu_cnt; index++) {
+		if (cpu_apic_info.apic_ids[index] < 0xff)
+			current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current,
+					index, cpu_apic_info.apic_ids[index]);
+		else
+			current += acpi_create_madt_lx2apic((acpi_madt_lx2apic_t *)current,
+					index, cpu_apic_info.apic_ids[index]);
+	}
+
+	return current;
+}
+
+unsigned long acpi_create_madt_lapics_with_nmis_hybrid(unsigned long current)
+{
+	const u16 flags = MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH;
+
+	current = acpi_create_madt_lapics_hybrid(current);
+
+	/* 1: LINT1 connect to NMI */
+	/* create all subtables for processors */
+	current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current,
+			ACPI_MADT_LAPIC_NMI_ALL_PROCESSORS, flags, 1);
+
+	if (!CONFIG(XAPIC_ONLY))
+		current += acpi_create_madt_lx2apic_nmi((acpi_madt_lx2apic_nmi_t *)current,
+				ACPI_MADT_LX2APIC_NMI_ALL_PROCESSORS, flags, 1);
+
+	return current;
+}
+
 static enum cpu_perf_eff_type get_core_type(void)
 {
 	return (get_soc_cpu_type() == CPUID_CORE_TYPE_INTEL_CORE) ?

src/soc/intel/common/block/include/intelblocks/acpi.h

@@ -18,6 +18,8 @@ enum core_type {
 	CPUID_UNKNOWN = 0xff,
 };
 
+unsigned long acpi_create_madt_lapics_with_nmis_hybrid(unsigned long current);
+
 /* Generates ACPI code to define _CPC control method */
 void acpigen_write_CPPC_hybrid_method(int core_id);