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google/fizz: correct memory rcomp settings 

Follow the schematic and Doc 573387 to correct the rcomp and
rcomp target settings for fizz

TEST= boot ok and the system can enter and resume from S3.

Change-Id: Iffa90461509cfadaca20e335a6655e549e79e749
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/22479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Kane Chen 2017-11-14 11:38:01 +08:00 committed by Shelley Chen
parent 6919a9376e
commit 73031bcce0
1 changed files with 2 additions and 2 deletions
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4
src/mainboard/google/fizz/romstage.c
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@ -24,9 +24,9 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig;
const FSPM_ARCH_UPD *arch_upd = &mupd->FspmArchUpd;
/* Rcomp resistor */
const u16 rcomp_resistor[] = { 200, 81, 162 };
const u16 rcomp_resistor[] = { 121, 81, 100 };
/* Rcomp target */
const u16 rcomp_target[] = { 100, 40, 40, 23, 40 };
const u16 rcomp_target[] = { 100, 40, 20, 20, 26 };
/* SPD was saved in S0/S5 path, skips it when resumes from S3 */
if (arch_upd->BootMode == FSP_BOOT_ON_S3_RESUME)