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ARMv7: Remove static CBMEM allocation 

The calculations for static allocation are no longer valid.

Change-Id: I6740cdcec789abddf78485a0edaf24882ef8c2a5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4569
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
This commit is contained in:
Kyösti Mälkki 2013-12-23 12:14:13 +02:00
parent c79dfdb991
commit 732cee31a6
5 changed files with 0 additions and 43 deletions
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4
src/cpu/samsung/exynos5250/Kconfig
View File

@ -88,10 +88,6 @@ config SYS_SDRAM_BASE
hex hex
default 0x40000000 default 0x40000000
config COREBOOT_TABLES_SIZE
hex
default 0x4000000
choice CONSOLE_SERIAL_UART_CHOICES choice CONSOLE_SERIAL_UART_CHOICES
prompt "Serial Console UART" prompt "Serial Console UART"
default CONSOLE_SERIAL_UART3 default CONSOLE_SERIAL_UART3

4
src/cpu/samsung/exynos5420/Kconfig
View File

@ -90,10 +90,6 @@ config SYS_SDRAM_BASE
hex hex
default 0x20000000 default 0x20000000
config COREBOOT_TABLES_SIZE
hex
default 0x4000000
choice CONSOLE_SERIAL_UART_CHOICES choice CONSOLE_SERIAL_UART_CHOICES
prompt "Serial Console UART" prompt "Serial Console UART"
default CONSOLE_SERIAL_UART3 default CONSOLE_SERIAL_UART3

5
src/cpu/ti/am335x/Kconfig
View File

@ -47,8 +47,3 @@ config CBFS_HEADER_ROM_OFFSET
config SYS_SDRAM_BASE config SYS_SDRAM_BASE
hex hex
default 0x40000000 default 0x40000000
# FIXME: this can probably be smaller
config COREBOOT_TABLES_SIZE
hex
default 0x800

15
src/mainboard/google/pit/mainboard.c
View File

@ -428,25 +428,10 @@ static void mainboard_init(device_t dev)
backlight_en(); backlight_en();
} }
#if !CONFIG_DYNAMIC_CBMEM
void get_cbmem_table(uint64_t *base, uint64_t *size)
{
*size = CONFIG_COREBOOT_TABLES_SIZE;
*base = CONFIG_SYS_SDRAM_BASE +
((unsigned)CONFIG_DRAM_SIZE_MB << 20ULL) -
CONFIG_COREBOOT_TABLES_SIZE;
}
#endif
static void mainboard_enable(device_t dev) static void mainboard_enable(device_t dev)
{ {
dev->ops->init = &mainboard_init; dev->ops->init = &mainboard_init;
#if !CONFIG_DYNAMIC_CBMEM
/* set up coreboot tables */
cbmem_initialize();
#endif
/* set up dcache and MMU */ /* set up dcache and MMU */
/* FIXME: this should happen via resource allocator */ /* FIXME: this should happen via resource allocator */
exynos5420_config_l2_cache(); exynos5420_config_l2_cache();

15
src/mainboard/google/snow/mainboard.c
View File

@ -265,25 +265,10 @@ static void mainboard_init(device_t dev)
// gpio_info(); // gpio_info();
} }
#if !CONFIG_DYNAMIC_CBMEM
void get_cbmem_table(uint64_t *base, uint64_t *size)
{
*size = CONFIG_COREBOOT_TABLES_SIZE;
*base = CONFIG_SYS_SDRAM_BASE +
((unsigned)CONFIG_DRAM_SIZE_MB << 20ULL) -
CONFIG_COREBOOT_TABLES_SIZE;
}
#endif
static void mainboard_enable(device_t dev) static void mainboard_enable(device_t dev)
{ {
dev->ops->init = &mainboard_init; dev->ops->init = &mainboard_init;
#if !CONFIG_DYNAMIC_CBMEM
/* set up coreboot tables */
cbmem_initialize();
#endif
/* set up dcache and MMU */ /* set up dcache and MMU */
/* FIXME: this should happen via resource allocator */ /* FIXME: this should happen via resource allocator */
exynos5250_config_l2_cache(); exynos5250_config_l2_cache();