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rk3288: add media 

BUG=chrome-os-partner:29778
TEST=Build coreboot

Change-Id: I74b30ecfe40c039855b835db0dfd0cd25adf960e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a30378a3152c930029a5b170cc6bf46180b5c7b8
Original-Change-Id: I5105e5277b8072c06bb41b39479373697ef81c67
Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/209468
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Tested-by: Lin Huang <hl@rock-chips.com>
Original-Commit-Queue: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/8860
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
This commit is contained in:
huang lin 2014-07-30 10:58:37 -07:00 committed by Patrick Georgi
parent 5a9b8f6aea
commit 7333e1fbc3
2 changed files with 11 additions and 2 deletions
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2
src/soc/rockchip/rk3288/Makefile.inc
View File

@ -31,10 +31,10 @@ bootblock-y += spi.c
romstage-y += cbmem.c romstage-y += cbmem.c
romstage-y += timer.c romstage-y += timer.c
romstage-y += monotonic_timer.c romstage-y += monotonic_timer.c
romstage-y += media.c
romstage-$(CONFIG_DRIVERS_UART) += uart.c romstage-$(CONFIG_DRIVERS_UART) += uart.c
romstage-y += clock.c romstage-y += clock.c
romstage-y += spi.c romstage-y += spi.c
romstage-y += media.c
ramstage-y += cbmem.c ramstage-y += cbmem.c
ramstage-y += timer.c ramstage-y += timer.c

11
src/soc/rockchip/rk3288/media.c
View File

@ -20,8 +20,17 @@
#include <cbfs.h> #include <cbfs.h>
#include <string.h> #include <string.h>
#include <console/console.h> #include <console/console.h>
#include "soc/rockchip/rk3288/spi.h"
int init_default_cbfs_media(struct cbfs_media *media) int init_default_cbfs_media(struct cbfs_media *media)
{ {
return 0; #if defined(__BOOT_BLOCK__)
return initialize_rockchip_spi_cbfs_media(media,
(void *)CONFIG_CBFS_SRAM_CACHE_ADDRESS,
CONFIG_CBFS_SRAM_CACHE_SIZE);
#else
return initialize_rockchip_spi_cbfs_media(media,
(void *)CONFIG_CBFS_DRAM_CACHE_ADDRESS,
CONFIG_CBFS_DRAM_CACHE_SIZE);
#endif
} }