diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c
index 5bc3412efa..ff881ac20e 100644
--- a/src/southbridge/intel/bd82x6x/pcie.c
+++ b/src/southbridge/intel/bd82x6x/pcie.c
@@ -13,6 +13,26 @@
 #include "chip.h"
 #include "pch.h"
 
+static const char *pch_pcie_acpi_name(const struct device *dev)
+{
+	ASSERT(dev);
+
+	if (PCI_SLOT(dev->path.pci.devfn) == 0x1c) {
+		static const char *names[] = { "RP01",
+				"RP02",
+				"RP03",
+				"RP04",
+				"RP05",
+				"RP06",
+				"RP07",
+				"RP08"};
+
+		return names[PCI_FUNC(dev->path.pci.devfn)];
+	}
+
+	return NULL;
+}
+
 static void pch_pcie_pm_early(struct device *dev)
 {
 	u16 link_width_p0, link_width_p4;
@@ -272,26 +292,6 @@ static void pch_pciexp_scan_bridge(struct device *dev)
 	pch_pcie_pm_late(dev);
 }
 
-static const char *pch_pcie_acpi_name(const struct device *dev)
-{
-	ASSERT(dev);
-
-	if (PCI_SLOT(dev->path.pci.devfn) == 0x1c) {
-		static const char *names[] = { "RP01",
-				"RP02",
-				"RP03",
-				"RP04",
-				"RP05",
-				"RP06",
-				"RP07",
-				"RP08"};
-
-		return names[PCI_FUNC(dev->path.pci.devfn)];
-	}
-
-	return NULL;
-}
-
 static struct device_operations device_ops = {
 	.read_resources		= pci_bus_read_resources,
 	.set_resources		= pci_dev_set_resources,