From 7340efcf1998e4197bb2403657efed16e5e4e620 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Tue, 23 Jun 2020 11:11:30 -0700 Subject: [PATCH] mb/google/zork: Configure GPIO_40 as drive low in sleep path This change configures GPIO_40 (NVME_AUX_RESET_L) as drive low in sleep path so that the PERST# to NVMe device keeps asserted until coreboot reconfigures it as high on S3 resume path. This is similar to the earlier change for PCIE_RST1_L but helps platforms that use NVME_AUX_RESET_L instead of PCIE_RST1_L. GPIO_40 lives in S5 domain, hence it retains state across S3 entry/exit. Signed-off-by: Furquan Shaikh Change-Id: Ie79e946eee8f393863630226ae2183e653030415 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2261117 Reviewed-by: Aaron Durbin Commit-Queue: Furquan Shaikh Tested-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/42935 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- .../google/zork/variants/baseboard/gpio_baseboard_common.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c index 1dd2dd5b89..aacf14b7c5 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c @@ -36,6 +36,8 @@ static const struct soc_amd_gpio gpio_sleep_table[] = { PAD_GPO(GPIO_5, LOW), /* PCIE_RST1_L */ PAD_GPO(GPIO_27, LOW), + /* NVME_AUX_RESET_L */ + PAD_GPO(GPIO_40, LOW), /* EN_PWR_CAMERA */ PAD_GPO(GPIO_76, LOW), };