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mb/pcengines/apu2: use AGESA 1.0.0.4 with adjusted AGESA header 

PC Engines apu2 platform uses AGESA 1.0.0.4, because upstream AGESA
1.0.0.A doesn't work on apu2 - the platform doesn't boot. To properly
utilize AGESA 1.0.0.4 we need to adjust AGESA header to state, which
is compatible with AGESA 1.0.0.4 version.

Cut out the changes introduced in CB:11225 exclusively for apu2 board.

TEST=boot PC Engines apu2 and launch Debian Linux

Change-Id: I3d85ee14e35dae8079e8d552b6530a3867f65876
Signed-off-by: Piotr Kleinschmidt <piotr.kleins@gmail.com>
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Piotr Kleinschmidt 2019-10-09 11:47:03 +02:00 committed by Nico Huber
parent eae254efb3
commit 7354605f86
2 changed files with 18 additions and 0 deletions
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10
src/mainboard/pcengines/apu2/Kconfig
View File

@ -114,4 +114,14 @@ config DIMM_SPD_SIZE
int
default 128
config AGESA_USE_1_0_0_4_HEADER
bool
default y
help
Due to a bug in AGESA 1.0.0.A affecting boards without UMA, it is
impossible to use the newest blob. Using an older 1.0.0.4 blob
workarounds the problem, however some headers changes between blob
revisions. This option removes the changes in headers introduced
with AGESA 1.0.0.A to fit the 1.0.0.4 revision.
endif # BOARD_PCENGINES_APU2

8
src/vendorcode/amd/pi/00730F01/AGESA.h
View File

@ -775,6 +775,7 @@ typedef enum {
DP_VS_0_4V_9_5DB = 0x18 ///< 0x18
} DP_FIXED_VOLT_SWING_TYPE;
#if CONFIG(AGESA_USE_1_0_0_4_HEADER)
/// Alternative DRAM MAC
typedef enum {
MAC_UNTESTEDMAC, ///< Assign 0 to Untested MAC
@ -785,6 +786,7 @@ typedef enum {
MAC_300k, ///< Assign 5 to 300k
MAC_200k, ///< Assign 6 to 200k
} DRAM_MAXIMUM_ACTIVATE_COUNT;
#endif
// Macro for statically initializing various structures
#define PCIE_ENGINE_DATA_INITIALIZER(mType, mStartLane, mEndLane) {mType, mStartLane, mEndLane}
@ -1547,7 +1549,9 @@ typedef struct _CH_TIMING_STRUCT {
///< 667 (MHz)
///< 800 (MHz)
///< and so on...
#if CONFIG(AGESA_USE_1_0_0_4_HEADER)
OUT UINT8 Mac; ///< Maximum Activate Count
#endif
OUT UINT8 CasL; ///< CAS latency DCT setting (busclocks)
OUT UINT8 Trcd; ///< DCT Trcd (busclocks)
OUT UINT8 Trp; ///< DCT Trp (busclocks)
@ -1803,6 +1807,7 @@ typedef struct _MEM_PARAMETER_STRUCT {
///<
///< @BldCfgItem{BLDCFG_MEMORY_POWER_DOWN}
#if CONFIG(AGESA_USE_1_0_0_4_HEADER)
// Dram Mac Default
IN UINT8 DramMacDefault; ///< Default Maximum Activate Count
@ -1818,6 +1823,7 @@ typedef struct _MEM_PARAMETER_STRUCT {
///< @BldCfgItem{BLDCFG_MEMORY_EXTENDED_TEMPERATURE_RANGE}
// Extended temperature range
#endif
// Online Spare
IN BOOLEAN EnableOnLineSpareCtl; ///< Chip Select Spare Control bit 0.
@ -2721,8 +2727,10 @@ typedef struct {
IN BOOLEAN CfgMemoryEnableNodeInterleaving; ///< Memory Enable Node Interleaving.
IN BOOLEAN CfgMemoryChannelInterleaving; ///< Memory Channel Interleaving.
IN BOOLEAN CfgMemoryPowerDown; ///< Memory Power Down.
#if CONFIG(AGESA_USE_1_0_0_4_HEADER)
IN UINT8 CfgMemoryMacDefault; ///< Memory DRAM MAC Default
IN BOOLEAN CfgMemoryExtendedTemperatureRange; ///< Memory Extended Temperature Range
#endif
IN UINT32 CfgPowerDownMode; ///< Power Down Mode.
IN BOOLEAN CfgOnlineSpare; ///< Online Spare.
IN BOOLEAN CfgMemoryParityEnable; ///< Memory Parity Enable.