From 7357f2a0ff13380410ff23da9ac0f8648e1319bf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Mon, 16 Oct 2023 15:32:59 +0200 Subject: [PATCH] soc/intel/alderlake: Fix incorrect microcode comments MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The microcode for RPL-S C0 and H0 is actually available, however, the name of the file contained a typo: 06-b7-05 vs 06-bf-05. Fix the typos in the comments. Moreover, the ADL-S C0/H0 microcode file 06-97-05 has the same sha256 sum as the equivalent RPL-S C0/H0 microcode file 06-bf-05. The sha256 sum of ADL-S/RPL-S C0/H0 microcode on intel-microcode tag microcode-20230808: 5d8d4a4d5456c43b7cc04937c80aec094ccbf3bd89f34ffa5182913ef944a9f9 Update the comments to correctly indicate supported CPU steppings. Change-Id: I4c848e0dfc40f6c8e26a9b31e7c4cf4c5a09128f Signed-off-by: Michał Żygowski Reviewed-on: https://review.coreboot.org/c/coreboot/+/78413 Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) --- src/soc/intel/alderlake/Makefile.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/alderlake/Makefile.inc b/src/soc/intel/alderlake/Makefile.inc index 1da9b3824e..55fc83ea7c 100644 --- a/src/soc/intel/alderlake/Makefile.inc +++ b/src/soc/intel/alderlake/Makefile.inc @@ -78,11 +78,11 @@ endif ifeq ($(CONFIG_SOC_INTEL_ALDERLAKE_PCH_S),y) # 06-97-00, 06-97-01, 06-97-04 are ADL-S Engineering Samples # 06-97-02 are ADL-S/HX Quality Samples but also ADL-HX Engineering Samples -# ADL-S/HX C0 and ADL-S H0 +# 06-b7-00 are RPL-S Engineering Samples +# ADL-S/HX C0/H0 and RPL-S C0/H0 cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-97-05 # RPL-S/HX B0 cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-b7-01 -# 06-b7-00, 06-b7-02, 06-b7-05 RPL-S/HX A0, C0 and H0 missing else ifeq ($(CONFIG_SOC_INTEL_ALDERLAKE_PCH_N),y) cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-be-00 else