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mb/google/volteer: Customize PCH VR settings for better Sx power savings 

For Volteer mainboard, this patch set optimized values for PCH external
VR settings and ext rail voltage/current, to achieve better power
savings in sleep states.

v1p05 and vnn power rails can be used as an alternative source
by-passing vccin_aux during Sx. This by-pass feature, enables us to
shutdown vccin_aux rail which is higher voltage rail compared to v1p05
and vnn. These both rails were disabled by default in FSP. Changes in
this patch are:

1. v1p05 and vnn rails are enabled and enabled supported voltage types
   in S0i1, S0i2, S0i3, S3, S4, S5 states. They were disabled by default.

2. Icc Max for v1p05 changed to 500 mA from default 100 mA.

3. vnn rail's voltage is changed to 5 V from default 4.2 V.

BUG=None
BRANCH=None
TEST="Build and boot volteer and check VR settings with Intel ITP-XDP
debugger and verify approx 250 mW power savings in Sx"

Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com>
Change-Id: Ib46423872c956af9aaa92902fce552d5447237c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42223
Reviewed-by: Venkata Krishna Nimmagadda <Venkata.krishna.nimmagadda@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Venkata Krishna Nimmagadda 2020-06-09 00:11:34 -07:00 committed by Tim Wawrzynczak
parent e18f71964d
commit 7368da32e7
1 changed files with 14 additions and 0 deletions
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14
src/mainboard/google/volteer/variants/baseboard/devicetree.cb
View File

@ -244,6 +244,20 @@ chip soc/intel/tigerlake
},
}"
register "ext_fivr_settings" = "{
.configure_ext_fivr = 1,
.v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX,
.vnn_enable_bitmap = FIVR_ENABLE_ALL_SX,
.v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL |
FIVR_VOLTAGE_MIN_ACTIVE |
FIVR_VOLTAGE_MIN_RETENTION,
.vnn_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL |
FIVR_VOLTAGE_MIN_ACTIVE |
FIVR_VOLTAGE_MIN_RETENTION,
.v1p05_icc_max_ma = 500,
.vnn_sx_voltage_mv = 1250,
}"
device domain 0 on
#From EDS(575683)
device pci 00.0 on end # Host Bridge 0x9A14:U/0x9A12:Y