diff --git a/src/cpu/amd/agesa/romstage.c b/src/cpu/amd/agesa/romstage.c
index cb98e7b6d3..a7d2ff90b7 100644
--- a/src/cpu/amd/agesa/romstage.c
+++ b/src/cpu/amd/agesa/romstage.c
@@ -26,6 +26,7 @@
 #include <romstage_handoff.h>
 #include <smp/node.h>
 #include <string.h>
+#include <timestamp.h>
 #include <northbridge/amd/agesa/agesa_helper.h>
 #include <northbridge/amd/agesa/state_machine.h>
 
@@ -60,6 +61,9 @@ void * asmlinkage romstage_main(unsigned long bist)
 
 	if ((initial_apic_id == 0) && boot_cpu()) {
 
+		timestamp_init(timestamp_get());
+		timestamp_add_now(TS_START_ROMSTAGE);
+
 		platform_once(cb);
 
 		console_init();
@@ -77,11 +81,17 @@ void * asmlinkage romstage_main(unsigned long bist)
 
 		agesa_execute_state(cb, AMD_INIT_EARLY);
 
+		timestamp_add_now(TS_BEFORE_INITRAM);
+
 		if (!cb->s3resume)
 			agesa_execute_state(cb, AMD_INIT_POST);
 		else
 			agesa_execute_state(cb, AMD_INIT_RESUME);
 
+		/* FIXME: Detect if TSC frequency changed during raminit? */
+		timestamp_rescale_table(1, 4);
+		timestamp_add_now(TS_AFTER_INITRAM);
+
 	} else {
 
 		agesa_main(cb);