kunimitsu: Modify DQ/DQS mapping
Modify DQ Byte Map and DQS Byte Swizzling to match up with design BUG=chrome-os-partner:44647 BRANCH=none TEST=System boot up and pass memory initialization Signed-off-by: Mike Hsieh <mike.m.hsieh@intel.com> Change-Id: I2018b9e6f8b557689d15acfe1f9404a9de5ae3bb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7d0a30d4b12bf4dc588d525399a8d223ff35e3de Original-Change-Id: I6001c853e4c5540717acf813e039c5c5dbe14c78 Original-Reviewed-on: https://chromium-review.googlesource.com/295518 Original-Commit-Ready: Wenkai Du <wenkai.du@intel.com> Original-Tested-by: Robbie Zhang <robbie.zhang@intel.com> Original-Reviewed-by: Robbie Zhang <robbie.zhang@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11551 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -29,12 +29,12 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
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const u8 dq_map[2][12] = {
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{0x0F, 0xF0 , 0x00, 0xF0 , 0x0F, 0xF0 ,
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0x0F, 0x00 , 0xFF, 0x00 , 0xFF, 0x00},
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{0x33, 0xCC , 0x00, 0xCC , 0x33, 0xCC ,
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0x33, 0x00 , 0xFF, 0x00 , 0xFF, 0x00} };
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/* DQS CPU<>DRAM map for sklrvp board */
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{0x0F, 0xF0 , 0x00, 0xF0 , 0x0F, 0xF0 ,
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0x0F, 0x00 , 0xFF, 0x00 , 0xFF, 0x00} };
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/* DQS CPU<>DRAM map for kunimitsu board */
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const u8 dqs_map[2][8] = {
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{0, 1, 3, 2, 4, 5, 6, 7},
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{1, 0, 4, 5, 2, 3, 6, 7} };
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{0, 1, 3, 2, 6, 5, 4, 7},
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{2, 3, 0, 1, 6, 7, 4, 5} };
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/* Rcomp resistor*/
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const u16 RcompResistor[3] = {200, 81, 162 };
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