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- See Issue Tracker id-15 "lnxi-patch-15". 

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2078 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Jason Schildt 2005-10-25 21:50:06 +00:00
parent f274d94360
commit 737253bf12
9 changed files with 18 additions and 18 deletions
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4
src/mainboard/tyan/s2875/Options.lb
View File

@ -130,10 +130,10 @@ default CONFIG_PCI_ROM_RUN=1
##
## enable CACHE_AS_RAM specifics
##
default USE_DCACHE_RAM=1
default USE_DCACHE_RAM=0
default DCACHE_RAM_BASE=0xcf000
default DCACHE_RAM_SIZE=0x1000
default CONFIG_USE_INIT=1
default CONFIG_USE_INIT=0
##
## Build code to setup a generic IOAPIC

4
src/mainboard/tyan/s2881/Options.lb
View File

@ -130,10 +130,10 @@ default CONFIG_PCI_ROM_RUN=1
##
## enable CACHE_AS_RAM specifics
##
default USE_DCACHE_RAM=1
default USE_DCACHE_RAM=0
default DCACHE_RAM_BASE=0xcf000
default DCACHE_RAM_SIZE=0x1000
default CONFIG_USE_INIT=1
default CONFIG_USE_INIT=0
##
## Build code to setup a generic IOAPIC

4
src/mainboard/tyan/s2882/Options.lb
View File

@ -130,10 +130,10 @@ default CONFIG_PCI_ROM_RUN=1
##
## enable CACHE_AS_RAM specifics
##
default USE_DCACHE_RAM=1
default USE_DCACHE_RAM=0
default DCACHE_RAM_BASE=0xcf000
default DCACHE_RAM_SIZE=0x1000
default CONFIG_USE_INIT=1
default CONFIG_USE_INIT=0
##
## Build code to setup a generic IOAPIC

4
src/mainboard/tyan/s2885/Options.lb
View File

@ -130,10 +130,10 @@ default CONFIG_PCI_ROM_RUN=1
##
## enable CACHE_AS_RAM specifics
##
default USE_DCACHE_RAM=1
default USE_DCACHE_RAM=0
default DCACHE_RAM_BASE=0xcf000
default DCACHE_RAM_SIZE=0x1000
default CONFIG_USE_INIT=1
default CONFIG_USE_INIT=0
##
## Build code to setup a generic IOAPIC

4
src/mainboard/tyan/s2891/Options.lb
View File

@ -139,10 +139,10 @@ default K8_E0_MEM_HOLE_SIZEK=0x100000
##
## enable CACHE_AS_RAM specifics
##
default USE_DCACHE_RAM=1
default USE_DCACHE_RAM=0
default DCACHE_RAM_BASE=0xcf000
default DCACHE_RAM_SIZE=0x1000
default CONFIG_USE_INIT=1
default CONFIG_USE_INIT=0
##

4
src/mainboard/tyan/s2892/Options.lb
View File

@ -139,10 +139,10 @@ default CONFIG_PCI_ROM_RUN=1
##
## enable CACHE_AS_RAM specifics
##
default USE_DCACHE_RAM=1
default USE_DCACHE_RAM=0
default DCACHE_RAM_BASE=0xcf000
default DCACHE_RAM_SIZE=0x1000
default CONFIG_USE_INIT=1
default CONFIG_USE_INIT=0
##

4
src/mainboard/tyan/s2895/Options.lb
View File

@ -136,10 +136,10 @@ default CONFIG_PCI_ROM_RUN=1
##
## enable CACHE_AS_RAM specifics
##
default USE_DCACHE_RAM=1
default USE_DCACHE_RAM=0
default DCACHE_RAM_BASE=0xcf000
default DCACHE_RAM_SIZE=0x1000
default CONFIG_USE_INIT=1
default CONFIG_USE_INIT=0
##
## Build code to setup a generic IOAPIC

4
src/mainboard/tyan/s4880/Options.lb
View File

@ -130,10 +130,10 @@ default CONFIG_PCI_ROM_RUN=1
##
## enable CACHE_AS_RAM specifics
##
default USE_DCACHE_RAM=1
default USE_DCACHE_RAM=0
default DCACHE_RAM_BASE=0xcf000
default DCACHE_RAM_SIZE=0x1000
default CONFIG_USE_INIT=1
default CONFIG_USE_INIT=0
##
## Build code to setup a generic IOAPIC

4
src/mainboard/tyan/s4882/Options.lb
View File

@ -130,10 +130,10 @@ default CONFIG_PCI_ROM_RUN=1
##
## enable CACHE_AS_RAM specifics
##
default USE_DCACHE_RAM=1
default USE_DCACHE_RAM=0
default DCACHE_RAM_BASE=0xcf000
default DCACHE_RAM_SIZE=0x1000
default CONFIG_USE_INIT=1
default CONFIG_USE_INIT=0
##
## Build code to setup a generic IOAPIC