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mb/intel/tglrvp: Enable Pcie WWAN m.2 

Enables Pcie M.2 support for WWAN and disable M.2 USB.
RP4 is already on and PcieRpEnable[3] is enabled. Clock source 2 is already
configured. Added missing gpio configuration.

BUG=none
TEST=Boot to OS, check WWAN functionality

Change-Id: Ie9b7915062b2ef65d881d478e64322c0b8765614
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45828
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Bora Guvendik 2020-08-28 10:50:47 -07:00 committed by Patrick Georgi
parent d1095c7ed7
commit 7377cda608
4 changed files with 20 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
View File

@ -20,7 +20,7 @@ chip soc/intel/tigerlake
register "SmbusEnable" = "1"
register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-C Port1
register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN
register "usb2_ports[1]" = "USB2_PORT_EMPTY" # M.2 WWAN
register "usb2_ports[2]" = "USB2_PORT_MID(OC3)" # M.2 Bluetooth
register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port1
register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-C Port2

9
src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c
View File

@ -104,6 +104,15 @@ static const struct pad_config early_gpio_table[] = {
PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1),
/* B22 : GSPI1_MOSI */
PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1),
/* WWAN */
PAD_CFG_GPO(GPP_H23, 1, DEEP), /* WWAN_PWREN */
PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), /* CLK SRC 2 */
PAD_CFG_GPI_SCI(GPP_C9, NONE, DEEP, LEVEL, INVERT), /* WWAN_WAKE_N */
PAD_CFG_GPO(GPP_C11, 1, DEEP), /* FULL_CARD_POWER_OFF_N */
PAD_CFG_GPO(GPP_C10, 1, DEEP), /* WWAN_RST_N */
PAD_CFG_GPO(GPP_B17, 1, DEEP), /* WWAN_PERST_N */
PAD_CFG_GPO(GPP_D15, 1, DEEP), /* WWAN_DISABLE_N */
};
const struct pad_config *variant_gpio_table(size_t *num)

2
src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
View File

@ -20,7 +20,7 @@ chip soc/intel/tigerlake
register "SmbusEnable" = "1"
register "usb2_ports[0]" = "USB2_PORT_MID(OC3)" # Type-C Port1
register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN
register "usb2_ports[1]" = "USB2_PORT_EMPTY" # M.2 WWAN
register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" # M.2 Bluetooth, USB3/2 Type A Port1
register "usb2_ports[3]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A Port 1
register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # Type-C Port2

9
src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c
View File

@ -100,6 +100,15 @@ static const struct pad_config early_gpio_table[] = {
PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1),
/* B22 : GSPI1_MOSI */
PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1),
/* WWAN */
PAD_CFG_GPO(GPP_D11, 1, DEEP), /* WWAN_PWREN */
PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), /* CLK SRC 2 */
PAD_CFG_GPI_SCI(GPP_C9, NONE, DEEP, LEVEL, INVERT), /* WWAN_WAKE_N */
PAD_CFG_GPO(GPP_C11, 1, DEEP), /* FULL_CARD_POWER_OFF_N */
PAD_CFG_GPO(GPP_C10, 1, DEEP), /* WWAN_RST_N */
PAD_CFG_GPO(GPP_B17, 1, DEEP), /* WWAN_PERST_N */
PAD_CFG_GPO(GPP_D15, 1, DEEP), /* WWAN_DISABLE_N */
};
const struct pad_config *variant_gpio_table(size_t *num)