mb/facebook/monolith: Enable the 2nd EC UART at 0x2f8
BUG=N/A TEST=tested on facebook monolith Change-Id: I36e652e66c66eeb770a5a5d987bb57c7eaa11382 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38749 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -11,6 +11,7 @@ config BOARD_SPECIFIC_OPTIONS
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select MAINBOARD_HAS_TPM2
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select MAINBOARD_HAS_TPM2
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select MAINBOARD_USES_IFD_GBE_REGION
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select MAINBOARD_USES_IFD_GBE_REGION
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select INTEL_GMA_HAVE_VBT
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select INTEL_GMA_HAVE_VBT
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select SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE
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config CBFS_SIZE
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config CBFS_SIZE
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hex "CBFS_SIZE"
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hex "CBFS_SIZE"
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@ -43,3 +43,28 @@ Device (COM1) {
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EndDependentFn ()
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EndDependentFn ()
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})
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})
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}
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}
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Device (COM2) {
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Name (_HID, EISAID ("PNP0501"))
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Name (_UID, 2)
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Method (_STA, 0, NotSerialized)
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{
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Return (0x0F)
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}
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Name (_CRS, ResourceTemplate ()
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{
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FixedIO (0x02F8, 0x08)
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IRQNoFlags () {3}
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})
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Name (_PRS, ResourceTemplate ()
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{
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StartDependentFn (0, 0) {
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FixedIO (0x02F8, 0x08)
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IRQNoFlags () {3}
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}
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EndDependentFn ()
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})
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}
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@ -19,11 +19,14 @@
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#include <device/pnp_ops.h>
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#include <device/pnp_ops.h>
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#include "onboard.h"
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#include "onboard.h"
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#define SERIAL_DEV PNP_DEV(ITE8528_CMD_PORT, 1) /* ITE8528 UART1 */
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#define SERIAL_DEV1 PNP_DEV(ITE8528_CMD_PORT, 1) /* ITE8528 UART1 */
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#define SERIAL_DEV2 PNP_DEV(ITE8528_CMD_PORT, 2) /* ITE8528 UART2 */
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void bootblock_mainboard_early_init(void)
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void bootblock_mainboard_early_init(void)
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{
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{
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/* Enable the serial port inside the EC */
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/* Enable the serial ports inside the EC */
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pnp_set_logical_device(SERIAL_DEV);
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pnp_set_logical_device(SERIAL_DEV1);
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pnp_set_enable(SERIAL_DEV, 1);
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pnp_set_enable(SERIAL_DEV1, 1);
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pnp_set_logical_device(SERIAL_DEV2);
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pnp_set_enable(SERIAL_DEV2, 1);
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}
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}
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