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nb/intel/sandybridge: Use bitfield for GDCRCMDPICODING 

This register's layout makes no sense, so use bitfields for clarity.

Tested on Asus P8H61-M PRO, still boots.

Change-Id: I61efc7349badc2c3297c9b71535dceecaba509d0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Angel Pons 2020-11-13 14:07:30 +01:00 committed by Felix Held
parent 8137806326
commit 737f111d2c
2 changed files with 31 additions and 7 deletions
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19
src/northbridge/intel/sandybridge/raminit_common.c
View File

@ -917,7 +917,7 @@ static const u32 lane_base[] = {
void program_timings(ramctr_timing *ctrl, int channel)
{
u32 reg32, reg_roundtrip_latency, reg_pi_code, reg_logic_delay, reg_io_latency;
u32 reg_roundtrip_latency, reg_pi_code, reg_logic_delay, reg_io_latency;
int lane;
int slotrank, slot;
int full_shift = 0;
@ -950,13 +950,18 @@ void program_timings(ramctr_timing *ctrl, int channel)
}
/* Enable CMD XOVER */
reg32 = get_XOVER_CMD(ctrl->rankmap[channel]);
reg32 |= (pi_coding_ctrl[0] & 0x3f) << 6;
reg32 |= (pi_coding_ctrl[0] & 0x40) << 9;
reg32 |= (pi_coding_ctrl[1] & 0x7f) << 18;
reg32 |= (full_shift & 0x3f) | ((full_shift & 0x40) << 6);
union gdcr_cmd_pi_coding_reg cmd_pi_coding = {
.raw = get_XOVER_CMD(ctrl->rankmap[channel]),
};
cmd_pi_coding.cmd_pi_code = full_shift & 0x3f;
cmd_pi_coding.cmd_logic_delay = !!(full_shift & 0x40);
MCHBAR32(GDCRCMDPICODING_ch(channel)) = reg32;
cmd_pi_coding.ctl_pi_code_d0 = pi_coding_ctrl[0] & 0x3f;
cmd_pi_coding.ctl_pi_code_d1 = pi_coding_ctrl[1] & 0x3f;
cmd_pi_coding.ctl_logic_delay_d0 = !!(pi_coding_ctrl[0] & 0x40);
cmd_pi_coding.ctl_logic_delay_d1 = !!(pi_coding_ctrl[1] & 0x40);
MCHBAR32(GDCRCMDPICODING_ch(channel)) = cmd_pi_coding.raw;
/* Enable CLK XOVER */
reg_pi_code = get_XOVER_CLK(ctrl->rankmap[channel]);

19
src/northbridge/intel/sandybridge/raminit_common.h
View File

@ -98,6 +98,25 @@ struct iosav_ssq {
} addr_update;
};
union gdcr_cmd_pi_coding_reg {
struct {
u32 cmd_pi_code : 6; /* [ 5.. 0] */
u32 ctl_pi_code_d0 : 6; /* [11.. 6] */
u32 cmd_logic_delay : 1; /* [12..12] */
u32 cmd_phase_delay : 1; /* [13..13] */
u32 cmd_xover_enable : 1; /* [14..14] */
u32 ctl_logic_delay_d0 : 1; /* [15..15] */
u32 ctl_phase_delay_d0 : 1; /* [16..16] */
u32 ctl_xover_enable_d0 : 1; /* [17..17] */
u32 ctl_pi_code_d1 : 6; /* [23..18] */
u32 ctl_logic_delay_d1 : 1; /* [24..24] */
u32 ctl_phase_delay_d1 : 1; /* [25..25] */
u32 ctl_xover_enable_d1 : 1; /* [26..26] */
u32 : 5;
};
u32 raw;
};
union tc_dbp_reg {
struct {
u32 tRCD : 4; /* [ 3.. 0] */