soc/intel/skylake: Use EBDA area to store cbmem_top address

This patch uses BIOS EBDA area to store relevent details
like cbmem top during romstage after MRC init is done.
Also provide provision to use the same EBDA data across
various stages without reexecuting memory map algorithm.

BRANCH=none
BUG=b:63974384
TEST=Ensures HW based memmap algorithm is executing once in romstage
and store required data into EBDA for other stage to avoid redundant
calculation and get cbmem_top start from EBDA area.

Change-Id: Ib1a674efa5ab3a4fc076fc93236edd911d28b398
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/soc/intel/skylake/Kconfig

@@ -54,6 +54,7 @@ config CPU_SPECIFIC_OPTIONS
 	select SOC_INTEL_COMMON_BLOCK
 	select SOC_INTEL_COMMON_BLOCK_CPU
 	select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
+	select SOC_INTEL_COMMON_BLOCK_EBDA
 	select SOC_INTEL_COMMON_BLOCK_FAST_SPI
 	select SOC_INTEL_COMMON_BLOCK_GSPI
 	select SOC_INTEL_COMMON_BLOCK_ITSS

src/soc/intel/skylake/include/soc/ebda.h

@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SOC_EBDA_H
+#define SOC_EBDA_H
+
+struct ebda_config {
+	uint32_t signature; /* 0x00 - EBDA signature */
+	uint32_t tolum_base; /* 0x04 - coreboot memory start */
+};
+
+#endif

src/soc/intel/skylake/memmap.c

@@ -14,12 +14,14 @@
  * GNU General Public License for more details.
  */
 
+#include <arch/ebda.h>
 #include <arch/io.h>
 #include <cbmem.h>
 #include <chip.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
+#include <intelblocks/ebda.h>
 #include <intelblocks/systemagent.h>
 #include <soc/msr.h>
 #include <soc/pci_devs.h>
@@ -274,6 +276,18 @@ static uintptr_t calculate_dram_base(void)
 	return dram_base;
 }
 
+/* Fill up memory layout information */
+void fill_soc_memmap_ebda(struct ebda_config *cfg)
+{
+	cfg->tolum_base = calculate_dram_base();
+}
+
+void cbmem_top_init(void)
+{
+	/* Fill up EBDA area */
+	fill_ebda_area();
+}
+
 /*
  *     +-------------------------+  Top of RAM (aligned)
  *     | System Management Mode  |
@@ -303,6 +317,9 @@ static uintptr_t calculate_dram_base(void)
  */
 void *cbmem_top(void)
 {
+	struct ebda_config ebda_cfg;
+	struct ebda_config *cfg = &ebda_cfg;
+
 	/*
 	 * Check if Tseg has been initialized, we will use this as a flag
 	 * to check if the MRC is done, and only then continue to read the
@@ -312,5 +329,7 @@ void *cbmem_top(void)
 	if (sa_get_tseg_base() == 0)
 		return NULL;
 
-	return (void *)calculate_dram_base();
+	read_ebda_data(cfg, sizeof(*cfg));
+
+	return (void *)(uintptr_t)cfg->tolum_base;
 }