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mb/intel/shadowmountain: Add the romstage code

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This patch includes the romstage changes for the
shadowmountain board.

BUG=b:175808146
TEST= Build and boot shadowmountain board till early ramstage.

Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: Ifd0bbcea9d4916d82bb1e3c275dd79d97a79727a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49731
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
V Sowmya 2021-01-20 07:15:37 +05:30 committed by Subrata Banik
parent 43f6598b27
commit 738aaa24d3
10 changed files with 203 additions and 0 deletions
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1
src/mainboard/intel/shadowmountain/Kconfig
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@ -15,6 +15,7 @@ config BOARD_SPECIFIC_OPTIONS
select EC_GOOGLE_CHROMEEC_LPC select EC_GOOGLE_CHROMEEC_LPC
select HAVE_ACPI_RESUME select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES select HAVE_ACPI_TABLES
select HAVE_SPD_IN_CBFS
select INTEL_LPSS_UART_FOR_CONSOLE select INTEL_LPSS_UART_FOR_CONSOLE
select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_CHROMEOS
select SOC_INTEL_ALDERLAKE select SOC_INTEL_ALDERLAKE

3
src/mainboard/intel/shadowmountain/Makefile.inc
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@ -6,8 +6,11 @@ bootblock-$(CONFIG_CHROMEOS) += chromeos.c
verstage-$(CONFIG_CHROMEOS) += chromeos.c verstage-$(CONFIG_CHROMEOS) += chromeos.c
romstage-$(CONFIG_CHROMEOS) += chromeos.c romstage-$(CONFIG_CHROMEOS) += chromeos.c
romstage-y += romstage.c
ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c
subdirs-y += spd
subdirs-y += variants/baseboard subdirs-y += variants/baseboard
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include

23
src/mainboard/intel/shadowmountain/romstage.c Normal file
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@ -0,0 +1,23 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <assert.h>
#include <console/console.h>
#include <fsp/api.h>
#include <soc/romstage.h>
#include <spd_bin.h>
#include <string.h>
#include <soc/meminit.h>
#include <baseboard/variants.h>
#include <cbfs.h>
void mainboard_memory_init_params(FSPM_UPD *mupd)
{
const struct mb_cfg *mem_config = variant_memory_params();
const bool half_populated = false;
const struct mem_spd lp5_spd_info = {
.topo = MEM_TOPO_MEMORY_DOWN,
.cbfs_index = variant_memory_sku(),
};
memcfg_init(&mupd->FspmConfig, mem_config, &lp5_spd_info, half_populated);
}

4
src/mainboard/intel/shadowmountain/spd/Makefile.inc Normal file
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@ -0,0 +1,4 @@
## SPDX-License-Identifier: GPL-2.0-only
SPD_SOURCES = shadowmountain_lp5_2gb # 0b000
SPD_SOURCES += shadowmountain_lp5_4gb # 0b001

32
src/mainboard/intel/shadowmountain/spd/shadowmountain_lp5_2gb.spd.hex Normal file
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@ -0,0 +1,32 @@
23 10 13 0E 15 1A 95 08 00 40 00 00 02 01 00 00
48 00 0A FF 92 55 05 00 AA 00 98 A8 90 90 06 C0
03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

32
src/mainboard/intel/shadowmountain/spd/shadowmountain_lp5_4gb.spd.hex Normal file
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@ -0,0 +1,32 @@
23 10 13 0E 15 1A B5 08 00 40 00 00 0A 01 00 00
48 00 0A FF 92 55 05 00 AA 00 98 A8 90 90 06 C0
03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

2
src/mainboard/intel/shadowmountain/variants/baseboard/Makefile.inc
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@ -1,3 +1,5 @@
## SPDX-License-Identifier: GPL-2.0-or-later ## SPDX-License-Identifier: GPL-2.0-or-later
bootblock-y += early_gpio.c bootblock-y += early_gpio.c
romstage-y += memory.c

22
src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
View file

@ -17,6 +17,28 @@ chip soc/intel/alderlake
register "gen2_dec" = "0x000c0201" register "gen2_dec" = "0x000c0201"
# EC memory map range is 0x900-0x9ff # EC memory map range is 0x900-0x9ff
register "gen3_dec" = "0x00fc0901" register "gen3_dec" = "0x00fc0901"
register "PrmrrSize" = "0"
# Enable PCH PCIE RP 5 using CLK 1
register "pch_pcie_rp[PCH_RP(5)]" = "{
.clk_src = 1,
.clk_req = 1,
.flags = PCIE_RP_CLK_REQ_DETECT,
}"
# Enable NVMe PCIE 9 using clk 0
register "pch_pcie_rp[PCH_RP(9)]" = "{
.clk_src = 0,
.clk_req = 0,
.flags = PCIE_RP_LTR,
}"
# Enable SD Card PCIE 8 using clk 3
register "pch_pcie_rp[PCH_RP(8)]" = "{
.clk_src = 3,
.clk_req = 3,
.flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR,
}"
device domain 0 on device domain 0 on
device pci 00.0 on end # Host Bridge device pci 00.0 on end # Host Bridge

3
src/mainboard/intel/shadowmountain/variants/baseboard/include/baseboard/variants.h
View file

@ -16,4 +16,7 @@ const struct cros_gpio *variant_cros_gpios(size_t *num);
void variant_configure_early_gpio_pads(void); void variant_configure_early_gpio_pads(void);
const struct mb_cfg *variant_memory_params(void);
int variant_memory_sku(void);
#endif /* __BASEBOARD_VARIANTS_H__ */ #endif /* __BASEBOARD_VARIANTS_H__ */

81
src/mainboard/intel/shadowmountain/variants/baseboard/memory.c Normal file
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@ -0,0 +1,81 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <baseboard/variants.h>
#include <gpio.h>
#include <soc/romstage.h>
static const struct mb_cfg lp5_mem_config = {
.type = MEM_TYPE_LP5X,
/* DQ CPU<>DRAM map */
.lpx_dq_map = {
.ddr0 = {
.dq0 = { 10, 8, 9, 12, 15, 13, 14, 11, }, /* DDR0_DQ0[7:0] */
.dq1 = { 2, 6, 3, 7, 5, 1, 4, 0, }, /* DDR0_DQ1[7:0] */
},
.ddr1 = {
.dq0 = { 2, 0, 3, 1, 6, 4, 7, 5, }, /* DDR1_DQ0[7:0] */
.dq1 = { 8, 9, 10, 11, 13, 12, 14, 15, }, /* DDR1_DQ1[7:0] */
},
.ddr2 = {
.dq0 = { 1, 0, 3, 2, 6, 4, 5, 7, }, /* DDR2_DQ0[7:0] */
.dq1 = { 12, 13, 8, 9, 15, 11, 14, 10, }, /* DDR2_DQ1[7:0] */
},
.ddr3 = {
.dq0 = { 8, 9, 11, 10, 13, 15, 14, 12, }, /* DDR3_DQ0[7:0] */
.dq1 = { 6, 5, 4, 7, 3, 2, 0, 1, }, /* DDR3_DQ1[7:0] */
},
.ddr4 = {
.dq0 = { 8, 13, 9, 12, 15, 11, 14, 10, }, /* DDR4_DQ0[7:0] */
.dq1 = { 2, 7, 3, 6, 5, 1, 4, 0, }, /* DDR4_DQ1[7:0] */
},
.ddr5 = {
.dq0 = { 0, 2, 1, 3, 6, 7, 4, 5, }, /* DDR5_DQ0[7:0] */
.dq1 = { 13, 12, 15, 14, 10, 9, 8, 11, }, /* DDR5_DQ1[7:0] */
},
.ddr6 = {
.dq0 = { 8, 13, 9, 12, 15, 10, 14, 11, }, /* DDR6_DQ0[7:0] */
.dq1 = { 3, 6, 2, 7, 4, 1, 0, 5, }, /* DDR6_DQ1[7:0] */
},
.ddr7 = {
.dq0 = { 11, 9, 10, 8, 12, 14, 13, 15, }, /* DDR7_DQ0[7:0] */
.dq1 = { 4, 6, 1, 0, 7, 3, 2, 5, } /* DDR7_DQ1[7:0] */
},
},
/* DQS CPU<>DRAM map */
.lpx_dqs_map = {
.ddr0 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR0_DQS[1:0] */
.ddr1 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR1_DQS[1:0] */
.ddr2 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR2_DQS[1:0] */
.ddr3 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR3_DQS[1:0] */
.ddr4 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR4_DQS[1:0] */
.ddr5 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR5_DQS[1:0] */
.ddr6 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR6_DQS[1:0] */
.ddr7 = { .dqs0 = 1, .dqs1 = 0 } /* DDR7_DQS[1:0] */
},
.ect = true, /* Early Command Training */
.UserBd = BOARD_TYPE_MOBILE,
.lp5x_config = {
.ccc_config = 0xD0,
},
};
const struct mb_cfg *variant_memory_params(void)
{
return &lp5_mem_config;
}
int variant_memory_sku(void)
{
const gpio_t spd_gpios[] = {
GPP_A7,
GPP_A20,
GPP_A19,
};
return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
}