mb/google/auron: Use Haswell CPU code
The VR config and S0ix options are now specified for the CPU chip. Change-Id: I75e405d41b4a0605e786fe761c92535e62d0cfce Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46945 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -1,6 +1,7 @@
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config BOARD_GOOGLE_BASEBOARD_AURON
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def_bool n
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select CPU_INTEL_HASWELL
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select SOC_INTEL_BROADWELL
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select BOARD_ROMSIZE_KB_8192
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select EC_GOOGLE_CHROMEEC
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@ -12,10 +12,13 @@ chip soc/intel/broadwell
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# Enable HDMI Hotplug with 6ms pulse
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register "gpu_dp_b_hotplug" = "0x06"
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register "s0ix_enable" = "1"
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device cpu_cluster 0 on
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device lapic 0 on end
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chip cpu/intel/haswell
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register "s0ix_enable" = "1"
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device lapic 0 on end
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device lapic 0xacac off end
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end
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end
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device domain 0 on
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@ -9,7 +9,14 @@ chip soc/intel/broadwell
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.backlight_pwm_hz = 200,
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}"
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register "s0ix_enable" = "0"
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device cpu_cluster 0 on
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chip cpu/intel/haswell
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register "s0ix_enable" = "0"
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device lapic 0 on end
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device lapic 0xacac off end
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end
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end
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device domain 0 on
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chip soc/intel/broadwell/pch
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@ -12,11 +12,20 @@ chip soc/intel/broadwell
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.backlight_pwm_hz = 200,
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}"
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register "vr_slow_ramp_rate_set" = "3"
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register "vr_slow_ramp_rate_enable" = "1"
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device cpu_cluster 0 on
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chip cpu/intel/haswell
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# Disable S0ix for now
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register "s0ix_enable" = "0"
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# Disable S0ix for now
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register "s0ix_enable" = "0"
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register "vr_config" = "{
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.slow_ramp_rate_set = 3,
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.slow_ramp_rate_enable = true,
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}"
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device lapic 0 on end
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device lapic 0xacac off end
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end
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end
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device domain 0 on
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chip soc/intel/broadwell/pch
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