mb/google/auron: Use Haswell CPU code

The VR config and S0ix options are now specified for the CPU chip.

Change-Id: I75e405d41b4a0605e786fe761c92535e62d0cfce
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46945
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/google/auron/Kconfig

@@ -1,6 +1,7 @@
 
 config BOARD_GOOGLE_BASEBOARD_AURON
 	def_bool n
+	select CPU_INTEL_HASWELL
 	select SOC_INTEL_BROADWELL
 	select BOARD_ROMSIZE_KB_8192
 	select EC_GOOGLE_CHROMEEC

src/mainboard/google/auron/devicetree.cb

@@ -12,10 +12,13 @@ chip soc/intel/broadwell
 	# Enable HDMI Hotplug with 6ms pulse
 	register "gpu_dp_b_hotplug" = "0x06"
 
-	register "s0ix_enable" = "1"
-
 	device cpu_cluster 0 on
-		device lapic 0 on end
+		chip cpu/intel/haswell
+			register "s0ix_enable" = "1"
+
+			device lapic 0 on end
+			device lapic 0xacac off end
+		end
 	end
 
 	device domain 0 on

src/mainboard/google/auron/variants/buddy/overridetree.cb

@@ -9,7 +9,14 @@ chip soc/intel/broadwell
 		.backlight_pwm_hz	= 200,
 	}"
 
-	register "s0ix_enable" = "0"
+	device cpu_cluster 0 on
+		chip cpu/intel/haswell
+			register "s0ix_enable" = "0"
+
+			device lapic 0 on end
+			device lapic 0xacac off end
+		end
+	end
 
 	device domain 0 on
 		chip soc/intel/broadwell/pch

src/mainboard/google/auron/variants/samus/overridetree.cb

@@ -12,11 +12,20 @@ chip soc/intel/broadwell
 		.backlight_pwm_hz	= 200,
 	}"
 
-	register "vr_slow_ramp_rate_set" = "3"
+	device cpu_cluster 0 on
-	register "vr_slow_ramp_rate_enable" = "1"
+		chip cpu/intel/haswell
+			# Disable S0ix for now
+			register "s0ix_enable" = "0"
 
-	# Disable S0ix for now
+			register "vr_config" = "{
-	register "s0ix_enable" = "0"
+				.slow_ramp_rate_set    = 3,
+				.slow_ramp_rate_enable = true,
+			}"
+
+			device lapic 0 on end
+			device lapic 0xacac off end
+		end
+	end
 
 	device domain 0 on
 		chip soc/intel/broadwell/pch