soc/intel/common/block/gspi: Recalculate BAR after resource allocation
The base address of the memory mapped I/O registers should not be cached across resource allocation. This CL will evict the cached value upon exiting the BS_DEV_RESOURCES stage. Change-Id: I81f2b5bfadbf1aaa3b38cca2bcc44ce521666821 Signed-off-by: jbk@chromium.org Reviewed-on: https://review.coreboot.org/c/coreboot/+/44084 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -2,6 +2,7 @@
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#include <device/mmio.h>
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#include <device/mmio.h>
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#include <assert.h>
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#include <assert.h>
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#include <bootstate.h>
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#include <console/console.h>
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#include <console/console.h>
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#include <delay.h>
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#include <delay.h>
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#include <device/device.h>
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#include <device/device.h>
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@ -257,6 +258,17 @@ static uintptr_t gspi_get_bus_base_addr(unsigned int gspi_bus)
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return gspi_base[gspi_bus];
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return gspi_base[gspi_bus];
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}
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}
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/*
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* PCI resource allocation will likely change the base address of the mapped
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* I/O registers. Clearing the cached value after the allocation step will
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* cause it to be recomputed by gspi_calc_base_addr() on next access.
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*/
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static void gspi_clear_cached_base(void *unused)
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{
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memset(gspi_base, 0, sizeof(gspi_base));
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}
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BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, gspi_clear_cached_base, NULL);
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/* Parameters for GSPI controller operation. */
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/* Parameters for GSPI controller operation. */
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struct gspi_ctrlr_params {
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struct gspi_ctrlr_params {
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uintptr_t mmio_base;
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uintptr_t mmio_base;
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