soc/intel/common/block/gspi: Recalculate BAR after resource allocation

The base address of the memory mapped I/O registers should not
be cached across resource allocation.  This CL will evict the cached
value upon exiting the BS_DEV_RESOURCES stage.

Change-Id: I81f2b5bfadbf1aaa3b38cca2bcc44ce521666821
Signed-off-by: jbk@chromium.org
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44084
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Jes Klinke 2020-07-31 09:48:35 -07:00 committed by Julius Werner
parent 89ed790028
commit 739c503404
1 changed files with 12 additions and 0 deletions

View File

@ -2,6 +2,7 @@
#include <device/mmio.h> #include <device/mmio.h>
#include <assert.h> #include <assert.h>
#include <bootstate.h>
#include <console/console.h> #include <console/console.h>
#include <delay.h> #include <delay.h>
#include <device/device.h> #include <device/device.h>
@ -257,6 +258,17 @@ static uintptr_t gspi_get_bus_base_addr(unsigned int gspi_bus)
return gspi_base[gspi_bus]; return gspi_base[gspi_bus];
} }
/*
* PCI resource allocation will likely change the base address of the mapped
* I/O registers. Clearing the cached value after the allocation step will
* cause it to be recomputed by gspi_calc_base_addr() on next access.
*/
static void gspi_clear_cached_base(void *unused)
{
memset(gspi_base, 0, sizeof(gspi_base));
}
BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, gspi_clear_cached_base, NULL);
/* Parameters for GSPI controller operation. */ /* Parameters for GSPI controller operation. */
struct gspi_ctrlr_params { struct gspi_ctrlr_params {
uintptr_t mmio_base; uintptr_t mmio_base;