* update quartet target to latest SMP changes.
* remove dead code from coherent_ht.c * add ldtstop code for link speed changes git-svn-id: svn://svn.coreboot.org/coreboot/trunk@991 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
parent
8275bad6f6
commit
73a9cf4ccb
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@ -1,225 +1,21 @@
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#define ASSEMBLY 1
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#include <stdint.h>
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#include <device/pci_def.h>
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#include "arch/romcc_io.h"
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#include <cpu/p6/apic.h>
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#include <arch/io.h>
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#include <device/pnp.h>
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#include <arch/romcc_io.h>
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#include "pc80/serial.c"
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#include "arch/i386/lib/console.c"
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#include "ram/ramtest.c"
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#include "northbridge/amd/amdk8/early_ht.c"
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#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
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#include "northbridge/amd/amdk8/raminit.h"
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static void print_debug_pci_dev(unsigned dev)
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{
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print_debug("PCI: ");
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print_debug_hex8((dev >> 16) & 0xff);
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print_debug_char(':');
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print_debug_hex8((dev >> 11) & 0x1f);
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print_debug_char('.');
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print_debug_hex8((dev >> 8) & 7);
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}
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static void print_pci_devices(void)
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{
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device_t dev;
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for(dev = PCI_DEV(0, 0, 0);
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dev <= PCI_DEV(0, 0x1f, 0x7);
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dev += PCI_DEV(0,0,1)) {
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uint32_t id;
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id = pci_read_config32(dev, PCI_VENDOR_ID);
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if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
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(((id >> 16) & 0xffff) == 0xffff) ||
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(((id >> 16) & 0xffff) == 0x0000)) {
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continue;
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}
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print_debug_pci_dev(dev);
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print_debug("\r\n");
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}
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}
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static void dump_pci_device(unsigned dev)
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{
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int i;
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print_debug_pci_dev(dev);
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print_debug("\r\n");
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for(i = 0; i <= 255; i++) {
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unsigned char val;
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if ((i & 0x0f) == 0) {
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print_debug_hex8(i);
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print_debug_char(':');
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}
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val = pci_read_config8(dev, i);
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print_debug_char(' ');
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print_debug_hex8(val);
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if ((i & 0x0f) == 0x0f) {
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print_debug("\r\n");
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}
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}
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}
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static void dump_pci_devices(void)
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{
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device_t dev;
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for(dev = PCI_DEV(0, 0, 0);
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dev <= PCI_DEV(0, 0x1f, 0x7);
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dev += PCI_DEV(0,0,1)) {
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uint32_t id;
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id = pci_read_config32(dev, PCI_VENDOR_ID);
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if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
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(((id >> 16) & 0xffff) == 0xffff) ||
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(((id >> 16) & 0xffff) == 0x0000)) {
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continue;
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}
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dump_pci_device(dev);
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}
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}
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static void dump_spd_registers(const struct mem_controller *ctrl)
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{
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int i;
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print_debug("\r\n");
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for(i = 0; i < 4; i++) {
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unsigned device;
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device = ctrl->channel0[i];
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if (device) {
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int j;
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print_debug("dimm: ");
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print_debug_hex8(i);
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print_debug(".0: ");
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print_debug_hex8(device);
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for(j = 0; j < 256; j++) {
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int status;
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unsigned char byte;
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if ((j & 0xf) == 0) {
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print_debug("\r\n");
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print_debug_hex8(j);
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print_debug(": ");
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}
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status = smbus_read_byte(device, j);
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if (status < 0) {
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print_debug("bad device\r\n");
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break;
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}
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byte = status & 0xff;
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print_debug_hex8(byte);
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print_debug_char(' ');
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}
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print_debug("\r\n");
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}
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device = ctrl->channel1[i];
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if (device) {
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int j;
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print_debug("dimm: ");
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print_debug_hex8(i);
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print_debug(".1: ");
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print_debug_hex8(device);
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for(j = 0; j < 256; j++) {
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int status;
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unsigned char byte;
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if ((j & 0xf) == 0) {
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print_debug("\r\n");
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print_debug_hex8(j);
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print_debug(": ");
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}
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status = smbus_read_byte(device, j);
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if (status < 0) {
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print_debug("bad device\r\n");
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break;
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}
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byte = status & 0xff;
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print_debug_hex8(byte);
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print_debug_char(' ');
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}
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print_debug("\r\n");
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}
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}
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}
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#warning "FIXME move these delay functions somewhere more appropriate"
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#warning "FIXME use the apic timer instead it needs no calibration on an Opteron it runs at 200Mhz"
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static void print_clock_multiplier(void)
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{
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msr_t msr;
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print_debug("clock multipler: 0x");
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msr = rdmsr(0xc0010042);
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print_debug_hex32(msr.lo & 0x3f);
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print_debug(" = 0x");
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print_debug_hex32(((msr.lo & 0x3f) + 8) * 100);
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print_debug("Mhz\r\n");
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}
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static unsigned usecs_to_ticks(unsigned usecs)
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{
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#warning "FIXME make usecs_to_ticks work properly"
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#if 1
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return usecs *2000;
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#else
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/* This can only be done if cpuid says fid changing is supported
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* I need to look up the base frequency another way for other
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* cpus. Is it worth dedicating a global register to this?
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* Are the PET timers useable for this purpose?
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*/
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msr_t msr;
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msr = rdmsr(0xc0010042);
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return ((msr.lo & 0x3f) + 8) * 100 *usecs;
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#endif
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}
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static void init_apic_timer(void)
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{
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volatile uint32_t *apic_reg = (volatile uint32_t *)0xfee00000;
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uint32_t start, end;
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/* Set the apic timer to no interrupts and periodic mode */
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apic_reg[0x320 >> 2] = (1 << 17)|(1<< 16)|(0 << 12)|(0 << 0);
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/* Set the divider to 1, no divider */
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apic_reg[0x3e0 >> 2] = (1 << 3) | 3;
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/* Set the initial counter to 0xffffffff */
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apic_reg[0x380 >> 2] = 0xffffffff;
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}
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static void udelay(unsigned usecs)
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{
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#if 1
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uint32_t start, ticks;
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tsc_t tsc;
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/* Calculate the number of ticks to run for */
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ticks = usecs_to_ticks(usecs);
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/* Find the current time */
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tsc = rdtsc();
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start = tsc.lo;
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do {
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tsc = rdtsc();
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} while((tsc.lo - start) < ticks);
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#else
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volatile uint32_t *apic_reg = (volatile uint32_t *)0xfee00000;
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uint32_t start, value, ticks;
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/* Calculate the number of ticks to run for */
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ticks = usecs * 200;
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start = apic_reg[0x390 >> 2];
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do {
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value = apic_reg[0x390 >> 2];
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} while((start - value) < ticks);
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#endif
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}
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static void mdelay(unsigned msecs)
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{
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int i;
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for(i = 0; i < msecs; i++) {
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udelay(1000);
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}
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}
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static void delay(unsigned secs)
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{
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int i;
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for(i = 0; i < secs; i++) {
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mdelay(1000);
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}
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}
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#include "cpu/k8/apic_timer.c"
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#include "lib/delay.c"
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#include "cpu/p6/boot_cpu.c"
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#include "northbridge/amd/amdk8/reset_test.c"
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#include "debug.c"
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static void memreset_setup(const struct mem_controller *ctrl)
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{
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@ -242,7 +38,6 @@ static void memreset(const struct mem_controller *ctrl)
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*
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*/
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static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
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{
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/* Routing Table Node i
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@ -291,6 +86,8 @@ static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
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return ret;
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}
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#include "northbridge/amd/amdk8/cpu_ldtstop.c"
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#include "southbridge/amd/amd8111/amd8111_ldtstop.c"
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#include "northbridge/amd/amdk8/raminit.c"
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#include "northbridge/amd/amdk8/coherent_ht.c"
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@ -298,112 +95,38 @@ static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
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#include "resourcemap.c" /* quartet does not want the default */
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#define NODE_ID 0x60
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#define HT_INIT_CONTROL 0x6c
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#define HTIC_ColdR_Detect (1<<4)
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#define HTIC_BIOSR_Detect (1<<5)
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#define HTIC_INIT_Detect (1<<6)
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static int boot_cpu(void)
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static void enable_lapic(void)
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{
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volatile unsigned long *local_apic;
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unsigned long apic_id;
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int bsp;
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msr_t msr;
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msr = rdmsr(0x1b);
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bsp = !!(msr.lo & (1 << 8));
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if (bsp) {
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print_debug("Bootstrap cpu\r\n");
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msr.hi &= 0xffffff00;
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msr.lo &= 0x000007ff;
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msr.lo |= APIC_DEFAULT_BASE | (1 << 11);
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wrmsr(0x1b, msr);
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}
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static void stop_this_cpu(void)
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{
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unsigned apicid;
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apicid = apic_read(APIC_ID) >> 24;
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/* Send an APIC INIT to myself */
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apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
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apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT);
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/* Wait for the ipi send to finish */
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apic_wait_icr_idle();
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/* Deassert the APIC INIT */
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apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
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apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT);
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/* Wait for the ipi send to finish */
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apic_wait_icr_idle();
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/* If I haven't halted spin forever */
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for(;;) {
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hlt();
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}
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return bsp;
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}
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static int cpu_init_detected(void)
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{
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unsigned long dcl;
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int cpu_init;
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unsigned long htic;
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htic = pci_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL);
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#if 0
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print_debug("htic: ");
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print_debug_hex32(htic);
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print_debug("\r\n");
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if (!(htic & HTIC_ColdR_Detect)) {
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print_debug("Cold Reset.\r\n");
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}
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if ((htic & HTIC_ColdR_Detect) && !(htic & HTIC_BIOSR_Detect)) {
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print_debug("BIOS generated Reset.\r\n");
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}
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if (htic & HTIC_INIT_Detect) {
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print_debug("Init event.\r\n");
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}
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#endif
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cpu_init = (htic & HTIC_INIT_Detect);
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if (cpu_init) {
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print_debug("CPU INIT Detected.\r\n");
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}
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return cpu_init;
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}
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static void pnp_write_config(unsigned char port, unsigned char value, unsigned char reg)
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{
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outb(reg, port);
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outb(value, port +1);
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}
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static unsigned char pnp_read_config(unsigned char port, unsigned char reg)
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{
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outb(reg, port);
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return inb(port +1);
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}
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static void pnp_set_logical_device(unsigned char port, int device)
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{
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pnp_write_config(port, device, 0x07);
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}
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|
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static void pnp_set_enable(unsigned char port, int enable)
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{
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pnp_write_config(port, enable?0x1:0x0, 0x30);
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}
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|
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static int pnp_read_enable(unsigned char port)
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{
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return !!pnp_read_config(port, 0x30);
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}
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|
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static void pnp_set_iobase0(unsigned char port, unsigned iobase)
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{
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pnp_write_config(port, (iobase >> 8) & 0xff, 0x60);
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pnp_write_config(port, iobase & 0xff, 0x61);
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}
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static void pnp_set_iobase1(unsigned char port, unsigned iobase)
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{
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pnp_write_config(port, (iobase >> 8) & 0xff, 0x62);
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pnp_write_config(port, iobase & 0xff, 0x63);
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}
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|
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static void pnp_set_irq0(unsigned char port, unsigned irq)
|
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{
|
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pnp_write_config(port, irq, 0x70);
|
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}
|
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|
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static void pnp_set_irq1(unsigned char port, unsigned irq)
|
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{
|
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pnp_write_config(port, irq, 0x72);
|
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}
|
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|
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static void pnp_set_drq(unsigned char port, unsigned drq)
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{
|
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pnp_write_config(port, drq & 0xff, 0x74);
|
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}
|
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|
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#define PC87360_FDC 0x00
|
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|
|
@ -464,48 +187,52 @@ static void main(void)
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.channel0 = { (0xa<<3)|12, (0xa<<3)|14, 0, 0 },
|
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.channel1 = { (0xa<<3)|13, (0xa<<3)|15, 0, 0 },
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};
|
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|
||||
|
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|
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if (cpu_init_detected()) {
|
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asm("jmp __cpu_reset");
|
||||
}
|
||||
pc87360_enable_serial();
|
||||
uart_init();
|
||||
console_init();
|
||||
if (boot_cpu() && !cpu_init_detected()) {
|
||||
#if 0
|
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init_apic_timer();
|
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#endif
|
||||
setup_quartet_resource_map();
|
||||
setup_coherent_ht_domain();
|
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enumerate_ht_chain();
|
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print_pci_devices();
|
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enable_smbus();
|
||||
#if 0
|
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dump_spd_registers(&cpu0);
|
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#endif
|
||||
sdram_initialize(&cpu0);
|
||||
|
||||
#if 1
|
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dump_pci_devices();
|
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#endif
|
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#if 0
|
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dump_pci_device(PCI_DEV(0, 0x18, 2));
|
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#endif
|
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|
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/* Check all of memory */
|
||||
#if 0
|
||||
msr_t msr;
|
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msr = rdmsr(TOP_MEM);
|
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print_debug("TOP_MEM: ");
|
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print_debug_hex32(msr.hi);
|
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print_debug_hex32(msr.lo);
|
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print_debug("\r\n");
|
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#endif
|
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#if 0
|
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ram_check(0x00000000, msr.lo);
|
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#else
|
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#if 1
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/* Check 16MB of memory */
|
||||
ram_check(0x00000000, 0x01000000);
|
||||
#endif
|
||||
#endif
|
||||
enable_lapic();
|
||||
if (!boot_cpu()) {
|
||||
stop_this_cpu();
|
||||
}
|
||||
init_timer();
|
||||
setup_default_resource_map();
|
||||
setup_coherent_ht_domain();
|
||||
enumerate_ht_chain(0);
|
||||
distinguish_cpu_resets();
|
||||
|
||||
#if 1
|
||||
print_pci_devices();
|
||||
#endif
|
||||
enable_smbus();
|
||||
#if 0
|
||||
dump_spd_registers(&cpu0);
|
||||
#endif
|
||||
sdram_initialize(&cpu0);
|
||||
|
||||
#if 1
|
||||
dump_pci_devices();
|
||||
#endif
|
||||
#if 0
|
||||
dump_pci_device(PCI_DEV(0, 0x18, 2));
|
||||
#endif
|
||||
|
||||
/* Check all of memory */
|
||||
#if 0
|
||||
msr_t msr;
|
||||
msr = rdmsr(TOP_MEM);
|
||||
print_debug("TOP_MEM: ");
|
||||
print_debug_hex32(msr.hi);
|
||||
print_debug_hex32(msr.lo);
|
||||
print_debug("\r\n");
|
||||
#endif
|
||||
#if 0
|
||||
ram_check(0x00000000, msr.lo);
|
||||
#else
|
||||
/* Check 16MB of memory */
|
||||
ram_check(0x00000000, 0x01000000);
|
||||
#endif
|
||||
}
|
||||
|
|
|
|||
|
|
@ -2,22 +2,37 @@
|
|||
#include <stdint.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <arch/io.h>
|
||||
#include "arch/romcc_io.h"
|
||||
#include "pc80/mc146818rtc_early.c"
|
||||
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
|
||||
#include "northbridge/amd/amdk8/early_ht.c"
|
||||
#include "cpu/p6/boot_cpu.c"
|
||||
#include "northbridge/amd/amdk8/reset_test.c"
|
||||
|
||||
static void main(void)
|
||||
{
|
||||
/* Nothing special needs to be done to find bus 0 */
|
||||
/* Allow the HT devices to be found */
|
||||
enumerate_ht_chain();
|
||||
enumerate_ht_chain(0);
|
||||
|
||||
/* Setup the 8111 */
|
||||
amd8111_enable_rom();
|
||||
|
||||
if (do_normal_boot()) {
|
||||
/* Jump to the normal image */
|
||||
/* Is this a cpu reset? */
|
||||
if (cpu_init_detected()) {
|
||||
if (last_boot_normal()) {
|
||||
asm("jmp __normal_image");
|
||||
} else {
|
||||
asm("jmp __cpu_reset");
|
||||
}
|
||||
}
|
||||
/* Is this a secondary cpu? */
|
||||
else if (!boot_cpu() && last_boot_normal()) {
|
||||
asm("jmp __normal_image");
|
||||
}
|
||||
/* This is the primary cpu how should I boot? */
|
||||
else if (do_normal_boot()) {
|
||||
asm("jmp __normal_image");
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -7,5 +7,5 @@
|
|||
|
||||
unsigned long initial_apicid[MAX_CPUS] =
|
||||
{
|
||||
0
|
||||
0, 1, 2, 3
|
||||
};
|
||||
|
|
|
|||
|
|
@ -77,11 +77,13 @@ static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
|
|||
return ret;
|
||||
}
|
||||
|
||||
#include "northbridge/amd/amdk8/cpu_ldtstop.c"
|
||||
#include "southbridge/amd/amd8111/amd8111_ldtstop.c"
|
||||
|
||||
#include "northbridge/amd/amdk8/raminit.c"
|
||||
#include "northbridge/amd/amdk8/coherent_ht.c"
|
||||
#include "sdram/generic_sdram.c"
|
||||
|
||||
|
||||
static void enable_lapic(void)
|
||||
{
|
||||
|
||||
|
|
|
|||
|
|
@ -1,333 +1,3 @@
|
|||
#if 0
|
||||
static void setup_coherent_ht_domain(void)
|
||||
{
|
||||
static const unsigned int register_values[] = {
|
||||
/* Routing Table Node i
|
||||
* F0:0x40 i = 0,
|
||||
* F0:0x44 i = 1,
|
||||
* F0:0x48 i = 2,
|
||||
* F0:0x4c i = 3,
|
||||
* F0:0x50 i = 4,
|
||||
* F0:0x54 i = 5,
|
||||
* F0:0x58 i = 6,
|
||||
* F0:0x5c i = 7
|
||||
* [ 0: 3] Request Route
|
||||
* [0] Route to this node
|
||||
* [1] Route to Link 0
|
||||
* [2] Route to Link 1
|
||||
* [3] Route to Link 2
|
||||
* [11: 8] Response Route
|
||||
* [0] Route to this node
|
||||
* [1] Route to Link 0
|
||||
* [2] Route to Link 1
|
||||
* [3] Route to Link 2
|
||||
* [19:16] Broadcast route
|
||||
* [0] Route to this node
|
||||
* [1] Route to Link 0
|
||||
* [2] Route to Link 1
|
||||
* [3] Route to Link 2
|
||||
*/
|
||||
PCI_ADDR(0, 0x18, 0, 0x40), 0xfff0f0f0, 0x00010101,
|
||||
PCI_ADDR(0, 0x18, 0, 0x44), 0xfff0f0f0, 0x00010101,
|
||||
PCI_ADDR(0, 0x18, 0, 0x48), 0xfff0f0f0, 0x00010101,
|
||||
PCI_ADDR(0, 0x18, 0, 0x4c), 0xfff0f0f0, 0x00010101,
|
||||
PCI_ADDR(0, 0x18, 0, 0x50), 0xfff0f0f0, 0x00010101,
|
||||
PCI_ADDR(0, 0x18, 0, 0x54), 0xfff0f0f0, 0x00010101,
|
||||
PCI_ADDR(0, 0x18, 0, 0x58), 0xfff0f0f0, 0x00010101,
|
||||
PCI_ADDR(0, 0x18, 0, 0x5c), 0xfff0f0f0, 0x00010101,
|
||||
|
||||
/* Hypetransport Transaction Control Register
|
||||
* F0:0x68
|
||||
* [ 0: 0] Disable read byte probe
|
||||
* 0 = Probes issues
|
||||
* 1 = Probes not issued
|
||||
* [ 1: 1] Disable Read Doubleword probe
|
||||
* 0 = Probes issued
|
||||
* 1 = Probes not issued
|
||||
* [ 2: 2] Disable write byte probes
|
||||
* 0 = Probes issued
|
||||
* 1 = Probes not issued
|
||||
* [ 3: 3] Disable Write Doubleword Probes
|
||||
* 0 = Probes issued
|
||||
* 1 = Probes not issued.
|
||||
* [ 4: 4] Disable Memroy Controller Target Start
|
||||
* 0 = TgtStart packets are generated
|
||||
* 1 = TgtStart packets are not generated.
|
||||
* [ 5: 5] CPU1 Enable
|
||||
* 0 = Second CPU disabled or not present
|
||||
* 1 = Second CPU enabled.
|
||||
* [ 6: 6] CPU Request PassPW
|
||||
* 0 = CPU requests do not pass posted writes
|
||||
* 1 = CPU requests pass posted writes.
|
||||
* [ 7: 7] CPU read Respons PassPW
|
||||
* 0 = CPU Responses do not pass posted writes
|
||||
* 1 = CPU responses pass posted writes.
|
||||
* [ 8: 8] Disable Probe Memory Cancel
|
||||
* 0 = Probes may generate MemCancels
|
||||
* 1 = Probes may not generate MemCancels
|
||||
* [ 9: 9] Disable Remote Probe Memory Cancel.
|
||||
* 0 = Probes hitting dirty blocks generate memory cancel packets
|
||||
* 1 = Only probed caches on the same node as the memory controller
|
||||
* generate cancel packets.
|
||||
* [10:10] Disable Fill Probe
|
||||
* 0 = Probes issued for cache fills
|
||||
* 1 = Probes not issued for cache fills.
|
||||
* [11:11] Response PassPw
|
||||
* 0 = Downstream response PassPW based on original request
|
||||
* 1 = Downstream response PassPW set to 1
|
||||
* [12:12] Change ISOC to Ordered
|
||||
* 0 = Bit 1 of coherent HT RdSz/WrSz command used for iosynchronous prioritization
|
||||
* 1 = Bit 1 of coherent HT RdSz/WrSz command used for ordering.
|
||||
* [14:13] Buffer Release Priority select
|
||||
* 00 = 64
|
||||
* 01 = 16
|
||||
* 10 = 8
|
||||
* 11 = 2
|
||||
* [15:15] Limit Coherent HT Configuration Space Range
|
||||
* 0 = No coherent HT configuration space restrictions
|
||||
* 1 = Limit coherent HT configuration space based on node count
|
||||
* [16:16] Local Interrupt Conversion Enable.
|
||||
* 0 = ExtInt/NMI interrups unaffected.
|
||||
* 1 = ExtInt/NMI broadcat interrupts converted to LINT0/1
|
||||
* [17:17] APIC Extended Broadcast Enable.
|
||||
* 0 = APIC broadcast is 0F
|
||||
* 1 = APIC broadcast is FF
|
||||
* [18:18] APIC Extended ID Enable
|
||||
* 0 = APIC ID is 4 bits.
|
||||
* 1 = APIC ID is 8 bits.
|
||||
* [19:19] APIC Extended Spurious Vector Enable
|
||||
* 0 = Lower 4 bits of spurious vector are read-only 1111
|
||||
* 1 = Lower 4 bits of spurious vecotr are writeable.
|
||||
* [20:20] Sequence ID Source Node Enable
|
||||
* 0 = Normal operation
|
||||
* 1 = Keep SeqID on routed packets for debugging.
|
||||
* [22:21] Downstream non-posted request limit
|
||||
* 00 = No limit
|
||||
* 01 = Limited to 1
|
||||
* 10 = Limited to 4
|
||||
* 11 = Limited to 8
|
||||
* [23:23] RESERVED
|
||||
* [25:24] Medium-Priority Bypass Count
|
||||
* - Maximum # of times a medium priority access can pass a low
|
||||
* priority access before Medium-Priority mode is disabled for one access.
|
||||
* [27:26] High-Priority Bypass Count
|
||||
* - Maximum # of times a high prioirty access can pass a medium or low
|
||||
* priority access before High-prioirty mode is disabled for one access.
|
||||
* [28:28] Enable High Priority CPU Reads
|
||||
* 0 = Cpu reads are medium prioirty
|
||||
* 1 = Cpu reads are high prioirty
|
||||
* [29:29] Disable Low Priority Writes
|
||||
* 0 = Non-isochronous writes are low priority
|
||||
* 1 = Non-isochronous writes are medium prioirty
|
||||
* [30:30] Disable High Priority Isochronous writes
|
||||
* 0 = Isochronous writes are high priority
|
||||
* 1 = Isochronous writes are medium priority
|
||||
* [31:31] Disable Medium Priority Isochronous writes
|
||||
* 0 = Isochronous writes are medium are high
|
||||
* 1 = With bit 30 set makes Isochrouns writes low priority.
|
||||
*/
|
||||
PCI_ADDR(0, 0x18, 0, 0x68), 0x00800000, 0x0f00840f,
|
||||
/* HT Initialization Control Register
|
||||
* F0:0x6C ok...
|
||||
* [ 0: 0] Routing Table Disable
|
||||
* 0 = Packets are routed according to routing tables
|
||||
* 1 = Packets are routed according to the default link field
|
||||
* [ 1: 1] Request Disable (BSP should clear this)
|
||||
* 0 = Request packets may be generated
|
||||
* 1 = Request packets may not be generated.
|
||||
* [ 3: 2] Default Link (Read-only)
|
||||
* 00 = LDT0
|
||||
* 01 = LDT1
|
||||
* 10 = LDT2
|
||||
* 11 = CPU on same node
|
||||
* [ 4: 4] Cold Reset
|
||||
* - Scratch bit cleared by a cold reset
|
||||
* [ 5: 5] BIOS Reset Detect
|
||||
* - Scratch bit cleared by a cold reset
|
||||
* [ 6: 6] INIT Detect
|
||||
* - Scratch bit cleared by a warm or cold reset not by an INIT
|
||||
*
|
||||
*/
|
||||
PCI_ADDR(0, 0x18, 0, 0x6C), 0xffffff8c, 0x00000000 | (1 << 6) |(1 << 5)| (1 << 4),
|
||||
/* LDTi Capabilities Registers
|
||||
* F0:0x80 i = 0,
|
||||
* F0:0xA0 i = 1,
|
||||
* F0:0xC0 i = 2,
|
||||
*/
|
||||
/* LDTi Link Control Registrs
|
||||
* F0:0x84 i = 0,
|
||||
* F0:0xA4 i = 1,
|
||||
* F0:0xC4 i = 2,
|
||||
* [ 1: 1] CRC Flood Enable
|
||||
* 0 = Do not generate sync packets on CRC error
|
||||
* 1 = Generate sync packets on CRC error
|
||||
* [ 2: 2] CRC Start Test (Read-Only)
|
||||
* [ 3: 3] CRC Force Frame Error
|
||||
* 0 = Do not generate bad CRC
|
||||
* 1 = Generate bad CRC
|
||||
* [ 4: 4] Link Failure
|
||||
* 0 = No link failure detected
|
||||
* 1 = Link failure detected
|
||||
* [ 5: 5] Initialization Complete
|
||||
* 0 = Initialization not complete
|
||||
* 1 = Initialization complete
|
||||
* [ 6: 6] Receiver off
|
||||
* 0 = Recevier on
|
||||
* 1 = Receiver off
|
||||
* [ 7: 7] Transmitter Off
|
||||
* 0 = Transmitter on
|
||||
* 1 = Transmitter off
|
||||
* [ 9: 8] CRC_Error
|
||||
* 00 = No error
|
||||
* [0] = 1 Error on byte lane 0
|
||||
* [1] = 1 Error on byte lane 1
|
||||
* [12:12] Isochrnous Enable (Read-Only)
|
||||
* [13:13] HT Stop Tristate Enable
|
||||
* 0 = Driven during an LDTSTOP_L
|
||||
* 1 = Tristated during and LDTSTOP_L
|
||||
* [14:14] Extended CTL Time
|
||||
* 0 = CTL is asserted for 16 bit times during link initialization
|
||||
* 1 = CTL is asserted for 50us during link initialization
|
||||
* [18:16] Max Link Width In (Read-Only?)
|
||||
* 000 = 8 bit link
|
||||
* 001 = 16bit link
|
||||
* [19:19] Doubleword Flow Control in (Read-Only)
|
||||
* 0 = This link does not support doubleword flow control
|
||||
* 1 = This link supports doubleword flow control
|
||||
* [22:20] Max Link Width Out (Read-Only?)
|
||||
* 000 = 8 bit link
|
||||
* 001 = 16bit link
|
||||
* [23:23] Doubleworld Flow Control out (Read-Only)
|
||||
* 0 = This link does not support doubleword flow control
|
||||
* 1 = This link supports doubleworkd flow control
|
||||
* [26:24] Link Width In
|
||||
* 000 = Use 8 bits
|
||||
* 001 = Use 16 bits
|
||||
* 010 = reserved
|
||||
* 011 = Use 32 bits
|
||||
* 100 = Use 2 bits
|
||||
* 101 = Use 4 bits
|
||||
* 110 = reserved
|
||||
* 111 = Link physically not connected
|
||||
* [27:27] Doubleword Flow Control In Enable
|
||||
* 0 = Doubleword flow control disabled
|
||||
* 1 = Doubleword flow control enabled (Not currently supported)
|
||||
* [30:28] Link Width Out
|
||||
* 000 = Use 8 bits
|
||||
* 001 = Use 16 bits
|
||||
* 010 = reserved
|
||||
* 011 = Use 32 bits
|
||||
* 100 = Use 2 bits
|
||||
* 101 = Use 4 bits
|
||||
* 110 = reserved
|
||||
* 111 = Link physically not connected
|
||||
* [31:31] Doubleworld Flow Control Out Enable
|
||||
* 0 = Doubleworld flow control disabled
|
||||
* 1 = Doubleword flow control enabled (Not currently supported)
|
||||
*/
|
||||
PCI_ADDR(0, 0x18, 0, 0x84), 0x00009c05, 0x11110020,
|
||||
/* LDTi Frequency/Revision Registers
|
||||
* F0:0x88 i = 0,
|
||||
* F0:0xA8 i = 1,
|
||||
* F0:0xC8 i = 2,
|
||||
* [ 4: 0] Minor Revision
|
||||
* Contains the HT Minor revision
|
||||
* [ 7: 5] Major Revision
|
||||
* Contains the HT Major revision
|
||||
* [11: 8] Link Frequency (Takes effect the next time the link is reconnected)
|
||||
* 0000 = 200Mhz
|
||||
* 0001 = reserved
|
||||
* 0010 = 400Mhz
|
||||
* 0011 = reserved
|
||||
* 0100 = 600Mhz
|
||||
* 0101 = 800Mhz
|
||||
* 0110 = 1000Mhz
|
||||
* 0111 = reserved
|
||||
* 1000 = reserved
|
||||
* 1001 = reserved
|
||||
* 1010 = reserved
|
||||
* 1011 = reserved
|
||||
* 1100 = reserved
|
||||
* 1101 = reserved
|
||||
* 1110 = reserved
|
||||
* 1111 = 100 Mhz
|
||||
* [15:12] Error (Not currently Implemented)
|
||||
* [31:16] Indicates the frequency capabilities of the link
|
||||
* [16] = 1 encoding 0000 of freq supported
|
||||
* [17] = 1 encoding 0001 of freq supported
|
||||
* [18] = 1 encoding 0010 of freq supported
|
||||
* [19] = 1 encoding 0011 of freq supported
|
||||
* [20] = 1 encoding 0100 of freq supported
|
||||
* [21] = 1 encoding 0101 of freq supported
|
||||
* [22] = 1 encoding 0110 of freq supported
|
||||
* [23] = 1 encoding 0111 of freq supported
|
||||
* [24] = 1 encoding 1000 of freq supported
|
||||
* [25] = 1 encoding 1001 of freq supported
|
||||
* [26] = 1 encoding 1010 of freq supported
|
||||
* [27] = 1 encoding 1011 of freq supported
|
||||
* [28] = 1 encoding 1100 of freq supported
|
||||
* [29] = 1 encoding 1101 of freq supported
|
||||
* [30] = 1 encoding 1110 of freq supported
|
||||
* [31] = 1 encoding 1111 of freq supported
|
||||
*/
|
||||
PCI_ADDR(0, 0x18, 0, 0x88), 0xfffff0ff, 0x00000200,
|
||||
/* LDTi Feature Capability
|
||||
* F0:0x8C i = 0,
|
||||
* F0:0xAC i = 1,
|
||||
* F0:0xCC i = 2,
|
||||
*/
|
||||
/* LDTi Buffer Count Registers
|
||||
* F0:0x90 i = 0,
|
||||
* F0:0xB0 i = 1,
|
||||
* F0:0xD0 i = 2,
|
||||
*/
|
||||
/* LDTi Bus Number Registers
|
||||
* F0:0x94 i = 0,
|
||||
* F0:0xB4 i = 1,
|
||||
* F0:0xD4 i = 2,
|
||||
* For NonCoherent HT specifies the bus number downstream (behind the host bridge)
|
||||
* [ 0: 7] Primary Bus Number
|
||||
* [15: 8] Secondary Bus Number
|
||||
* [23:15] Subordiante Bus Number
|
||||
* [31:24] reserved
|
||||
*/
|
||||
PCI_ADDR(0, 0x18, 0, 0x94), 0xff000000, 0x00ff0000,
|
||||
/* LDTi Type Registers
|
||||
* F0:0x98 i = 0,
|
||||
* F0:0xB8 i = 1,
|
||||
* F0:0xD8 i = 2,
|
||||
*/
|
||||
};
|
||||
int i;
|
||||
int max;
|
||||
print_debug("setting up coherent ht domain....\r\n");
|
||||
max = sizeof(register_values)/sizeof(register_values[0]);
|
||||
for(i = 0; i < max; i += 3) {
|
||||
device_t dev;
|
||||
unsigned where;
|
||||
unsigned long reg;
|
||||
#if 0
|
||||
print_debug_hex32(register_values[i]);
|
||||
print_debug(" <-");
|
||||
print_debug_hex32(register_values[i+2]);
|
||||
print_debug("\r\n");
|
||||
#endif
|
||||
dev = register_values[i] & ~0xff;
|
||||
where = register_values[i] & 0xff;
|
||||
reg = pci_read_config32(dev, where);
|
||||
reg &= register_values[i+1];
|
||||
reg |= register_values[i+2];
|
||||
pci_write_config32(dev, where, reg);
|
||||
#if 0
|
||||
reg = pci_read_config32(register_values[i]);
|
||||
reg &= register_values[i+1];
|
||||
reg |= register_values[i+2] & ~register_values[i+1];
|
||||
pci_write_config32(register_values[i], reg);
|
||||
#endif
|
||||
}
|
||||
print_debug("done.\r\n");
|
||||
}
|
||||
#else
|
||||
/* coherent hypertransport initialization for AMD64
|
||||
* written by Stefan Reinauer <stepan@openbios.info>
|
||||
* (c) 2003 by SuSE Linux AG
|
||||
|
|
@ -343,13 +13,12 @@ static void setup_coherent_ht_domain(void)
|
|||
*
|
||||
*/
|
||||
|
||||
#if 0
|
||||
#include "compat.h"
|
||||
#endif
|
||||
|
||||
#include <device/pci_def.h>
|
||||
#include "arch/romcc_io.h"
|
||||
|
||||
/*
|
||||
*
|
||||
*/
|
||||
|
||||
/* when generating a temporary row configuration we
|
||||
* don't want broadcast to be enabled for that node.
|
||||
|
|
@ -493,62 +162,6 @@ static bool check_connection(u8 src, u8 dest, u8 link)
|
|||
return 1;
|
||||
}
|
||||
|
||||
#if 0
|
||||
static unsigned int generate_row(u8 node, u8 row, u8 maxnodes)
|
||||
{
|
||||
/* Routing Table Node i
|
||||
*
|
||||
* F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c
|
||||
* i: 0, 1, 2, 3, 4, 5, 6, 7
|
||||
*
|
||||
* [ 0: 3] Request Route
|
||||
* [0] Route to this node
|
||||
* [1] Route to Link 0
|
||||
* [2] Route to Link 1
|
||||
* [3] Route to Link 2
|
||||
* [11: 8] Response Route
|
||||
* [0] Route to this node
|
||||
* [1] Route to Link 0
|
||||
* [2] Route to Link 1
|
||||
* [3] Route to Link 2
|
||||
* [19:16] Broadcast route
|
||||
* [0] Route to this node
|
||||
* [1] Route to Link 0
|
||||
* [2] Route to Link 1
|
||||
* [3] Route to Link 2
|
||||
*/
|
||||
|
||||
u32 ret=DEFAULT;
|
||||
|
||||
static const unsigned int rows_2p[2][2] = {
|
||||
{ 0x00050101, 0x00010404 },
|
||||
{ 0x00010404, 0x00050101 }
|
||||
};
|
||||
|
||||
static const unsigned int rows_4p[4][4] = {
|
||||
{ 0x00070101, 0x00010404, 0x00050202, 0x00010402 },
|
||||
{ 0x00010808, 0x000b0101, 0x00010802, 0x00090202 },
|
||||
{ 0x00090202, 0x00010802, 0x000b0101, 0x00010808 },
|
||||
{ 0x00010402, 0x00050202, 0x00010404, 0x00070101 }
|
||||
};
|
||||
|
||||
if (!(node>=maxnodes || row>=maxnodes)) {
|
||||
if (maxnodes==2)
|
||||
ret=rows_2p[node][row];
|
||||
if (maxnodes==4)
|
||||
ret=rows_4p[node][row];
|
||||
}
|
||||
|
||||
#if 0
|
||||
printk_spew("generating entry n=%d, r=%d, max=%d - row=%x\n",
|
||||
node,row,maxnodes,ret);
|
||||
#endif
|
||||
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
static void fill_row(u8 node, u8 row, u32 value)
|
||||
{
|
||||
#if 0
|
||||
|
|
@ -835,5 +448,3 @@ static int setup_coherent_ht_domain(void)
|
|||
|
||||
return reset_needed;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue