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There are more than a dozen targets in the v2 tree which refer to ROMCC 

in their Config.lb but never use it. There's no point in keeping dead
code around. Kill it.

This patch removes ROMCC remainders from Config.lb for tyan/s2735 and
tyan/s2850.

Abuild build log with and without the patch is completely identical.

More patches of the same type can be done, hopefully making
ROMCC dependencies a bit more clear for v2.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4048 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Carl-Daniel Hailfinger 2009-04-03 02:18:23 +00:00
parent e729846b64
commit 73ad326452
2 changed files with 0 additions and 114 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

56
src/mainboard/tyan/s2735/Config.lb
View File

@ -35,7 +35,6 @@ default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
arch i386 end arch i386 end
## ##
## Build the objects we have code for in this directory. ## Build the objects we have code for in this directory.
## ##
@ -44,8 +43,6 @@ driver mainboard.o
if HAVE_MP_TABLE object mptable.o end if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end if HAVE_PIRQ_TABLE object irq_tables.o end
object reset.o object reset.o
if USE_DCACHE_RAM
if CONFIG_USE_INIT if CONFIG_USE_INIT
makerule ./auto.o makerule ./auto.o
@ -62,31 +59,6 @@ makerule ./auto.inc
action "perl -e 's/\.text/.section .rom.text/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
end end
end
else
##
## Romcc output
##
makerule ./failover.E
depends "$(MAINBOARD)/failover.c ../romcc"
action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./failover.inc
depends "$(MAINBOARD)/failover.c ../romcc"
action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./auto.E
depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
action "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
action "../romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
end end
## ##
@ -95,7 +67,6 @@ end
mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/16bit/entry16.lds
if USE_DCACHE_RAM
if CONFIG_USE_INIT if CONFIG_USE_INIT
ldscript /cpu/x86/32bit/entry32.lds ldscript /cpu/x86/32bit/entry32.lds
end end
@ -103,7 +74,6 @@ if USE_DCACHE_RAM
if CONFIG_USE_INIT if CONFIG_USE_INIT
ldscript /cpu/x86/car/cache_as_ram.lds ldscript /cpu/x86/car/cache_as_ram.lds
end end
end
## ##
@ -117,24 +87,16 @@ else
ldscript /cpu/x86/32bit/reset32.lds ldscript /cpu/x86/32bit/reset32.lds
end end
if USE_DCACHE_RAM
else
### Should this be in the northbridge code?
mainboardinit arch/i386/lib/cpu_reset.inc
end
## ##
## Include an id string (For safe flashing) ## Include an id string (For safe flashing)
## ##
mainboardinit arch/i386/lib/id.inc mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds ldscript /arch/i386/lib/id.lds
if USE_DCACHE_RAM
## ##
## Setup Cache-As-Ram ## Setup Cache-As-Ram
## ##
mainboardinit cpu/x86/car/cache_as_ram.inc mainboardinit cpu/x86/car/cache_as_ram.inc
end
### ###
### This is the early phase of coreboot startup ### This is the early phase of coreboot startup
@ -142,36 +104,18 @@ end
### failover to another image. ### failover to another image.
### ###
if USE_FALLBACK_IMAGE if USE_FALLBACK_IMAGE
if USE_DCACHE_RAM
ldscript /arch/i386/lib/failover.lds ldscript /arch/i386/lib/failover.lds
else
ldscript /arch/i386/lib/failover.lds
mainboardinit ./failover.inc
end
end end
## ##
## Setup RAM ## Setup RAM
## ##
if USE_DCACHE_RAM
if CONFIG_USE_INIT if CONFIG_USE_INIT
initobject auto.o initobject auto.o
else else
mainboardinit ./auto.inc mainboardinit ./auto.inc
end end
else
# ROMCC
mainboardinit cpu/x86/fpu/enable_fpu.inc
mainboardinit cpu/x86/mmx/enable_mmx.inc
mainboardinit cpu/x86/sse/enable_sse.inc
mainboardinit ./auto.inc
mainboardinit cpu/x86/sse/disable_sse.inc
mainboardinit cpu/x86/mmx/disable_mmx.inc
end
## ##
## Include the secondary Configuration files ## Include the secondary Configuration files
## ##

58
src/mainboard/tyan/s2850/Config.lb
View File

@ -45,8 +45,6 @@ driver mainboard.o
if HAVE_MP_TABLE object mptable.o end if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end if HAVE_PIRQ_TABLE object irq_tables.o end
if USE_DCACHE_RAM
if CONFIG_USE_INIT if CONFIG_USE_INIT
makerule ./auto.o makerule ./auto.o
@ -63,31 +61,6 @@ makerule ./auto.inc
action "perl -e 's/\.text/.section .rom.text/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
end end
end
else
##
## Romcc output
##
makerule ./failover.E
depends "$(MAINBOARD)/failover.c ../romcc"
action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./failover.inc
depends "$(MAINBOARD)/failover.c ../romcc"
action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./auto.E
depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
action "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
action "../romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
end end
## ##
## Build our 16 bit and 32 bit coreboot entry code ## Build our 16 bit and 32 bit coreboot entry code
@ -99,7 +72,6 @@ end
mainboardinit cpu/x86/32bit/entry32.inc mainboardinit cpu/x86/32bit/entry32.inc
if USE_DCACHE_RAM
if CONFIG_USE_INIT if CONFIG_USE_INIT
ldscript /cpu/x86/32bit/entry32.lds ldscript /cpu/x86/32bit/entry32.lds
end end
@ -107,7 +79,6 @@ if USE_DCACHE_RAM
if CONFIG_USE_INIT if CONFIG_USE_INIT
ldscript /cpu/amd/car/cache_as_ram.lds ldscript /cpu/amd/car/cache_as_ram.lds
end end
end
## ##
## Build our reset vector (This is where coreboot is entered) ## Build our reset vector (This is where coreboot is entered)
@ -120,24 +91,16 @@ else
ldscript /cpu/x86/32bit/reset32.lds ldscript /cpu/x86/32bit/reset32.lds
end end
if USE_DCACHE_RAM
else
### Should this be in the northbridge code?
mainboardinit arch/i386/lib/cpu_reset.inc
end
## ##
## Include an id string (For safe flashing) ## Include an id string (For safe flashing)
## ##
mainboardinit arch/i386/lib/id.inc mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds ldscript /arch/i386/lib/id.lds
if USE_DCACHE_RAM
## ##
## Setup Cache-As-Ram ## Setup Cache-As-Ram
## ##
mainboardinit cpu/amd/car/cache_as_ram.inc mainboardinit cpu/amd/car/cache_as_ram.inc
end
### ###
### This is the early phase of coreboot startup ### This is the early phase of coreboot startup
@ -145,12 +108,7 @@ end
### failover to another image. ### failover to another image.
### ###
if USE_FALLBACK_IMAGE if USE_FALLBACK_IMAGE
if USE_DCACHE_RAM
ldscript /arch/i386/lib/failover.lds ldscript /arch/i386/lib/failover.lds
else
ldscript /arch/i386/lib/failover.lds
mainboardinit ./failover.inc
end
end end
### ###
@ -160,28 +118,12 @@ end
## ##
## Setup RAM ## Setup RAM
## ##
if USE_DCACHE_RAM
if CONFIG_USE_INIT if CONFIG_USE_INIT
initobject auto.o initobject auto.o
else else
mainboardinit ./auto.inc mainboardinit ./auto.inc
end end
else
##
## Setup RAM
##
mainboardinit cpu/x86/fpu/enable_fpu.inc
mainboardinit cpu/x86/mmx/enable_mmx.inc
mainboardinit cpu/x86/sse/enable_sse.inc
mainboardinit ./auto.inc
mainboardinit cpu/x86/sse/disable_sse.inc
mainboardinit cpu/x86/mmx/disable_mmx.inc
end
## ##
## Include the secondary Configuration files ## Include the secondary Configuration files
## ##