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google/cyan: Switch Touchpad and Touchscreen interrupts to be level-triggered 

Adapted from chromium commit 126d352
[Strago: switch Touchpad and Touchscreen interrupts to be level-triggered]

The Elan and other touch controllers found in this device work much
more reliably if used with level-triggered interrupts rather than
edge-triggered.

TEST=Boot several cyan boards, verify that touchpad and touchscreen
work.

Original-Change-Id: I59d05d9dfa9c41e5472d756ef51f0817a503c889
Original-Signed-off-by: Dmitry Torokhov <dtor@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/894689
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: Ia4f8cf83351dae0d78995ce0b0ed902d1e4ac3e8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Matt DeVillier 2018-07-31 16:41:06 -05:00 committed by Patrick Georgi
parent 6444d7df0b
commit 73b723d7db
13 changed files with 25 additions and 24 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/google/cyan/acpi/trackpad_atmel.asl
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@ -33,7 +33,7 @@ Scope (\_SB.PCI0.I2C6)
AddressingMode7Bit, // AddressingMode
"\\_SB.PCI0.I2C6", // ResourceSource
)
GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,,
GpioInt (Level, ActiveLow, ExclusiveAndWake, PullNone,,
"\\_SB.GPNC") { BOARD_TRACKPAD_GPIO_INDEX }
})

4
src/mainboard/google/cyan/variants/banon/gpio.c
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@ -161,9 +161,9 @@ static const struct soc_gpio_map gpn_gpio_map[] = {
GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */
GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA),
/* 17 GPIO_SUS3 */
GPI(trig_edge_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA),
GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA),
/* 18 GPIO_SUS7 */
GPI(trig_edge_low, L3, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA),
GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA),
/* 19 GPIO_SUS1 */
GPIO_NC, /* 20 GPIO_SUS5 */
GPIO_NC, /* 21 SEC_GPIO_SUS11 */

2
src/mainboard/google/cyan/variants/celes/gpio.c
View File

@ -164,7 +164,7 @@ static const struct soc_gpio_map gpn_gpio_map[] = {
GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */
GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA),
/* 17 GPIO_SUS3 */
GPI(trig_edge_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA),
GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA),
/* 18 GPIO_SUS7 */
GPIO_NC,
/* 19 GPIO_SUS1 */

4
src/mainboard/google/cyan/variants/cyan/gpio.c
View File

@ -162,9 +162,9 @@ static const struct soc_gpio_map gpn_gpio_map[] = {
GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */
GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA),
/* 17 GPIO_SUS3 */
GPI(trig_edge_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA),
GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA),
/* 18 GPIO_SUS7 */
GPI(trig_edge_low, L3, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA),
GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA),
/* 19 GPIO_SUS1 */
GPIO_NC, /* 20 GPIO_SUS5 */
GPIO_NC, /* 21 SEC_GPIO_SUS11 */

2
src/mainboard/google/cyan/variants/edgar/gpio.c
View File

@ -161,7 +161,7 @@ static const struct soc_gpio_map gpn_gpio_map[] = {
GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */
GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA),
/* 17 GPIO_SUS3 */
GPI(trig_edge_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA),
GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA),
/* 18 GPIO_SUS7 */
GPIO_NC, /* 19 GPIO_SUS1 */
GPIO_NC, /* 20 GPIO_SUS5 */

4
src/mainboard/google/cyan/variants/kefka/gpio.c
View File

@ -161,9 +161,9 @@ static const struct soc_gpio_map gpn_gpio_map[] = {
GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */
GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA),
/* 17 GPIO_SUS3 */
GPI(trig_edge_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA),
GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA),
/* 18 GPIO_SUS7 */
GPI(trig_edge_low, L3, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA),
GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA),
/* 19 GPIO_SUS1 */
GPIO_NC, /* 20 GPIO_SUS5 */
GPIO_NC, /* 21 SEC_GPIO_SUS11 */

4
src/mainboard/google/cyan/variants/reks/gpio.c
View File

@ -163,9 +163,9 @@ static const struct soc_gpio_map gpn_gpio_map[] = {
GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */
GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA),
/* 17 GPIO_SUS3 */
GPI(trig_edge_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA),
GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA),
/* 18 GPIO_SUS7 */
GPI(trig_edge_low, L3, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA),
GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA),
/* 19 GPIO_SUS1 */
GPIO_NC, /* 20 GPIO_SUS5 */
GPIO_NC, /* 21 SEC_GPIO_SUS11 */

4
src/mainboard/google/cyan/variants/relm/gpio.c
View File

@ -164,9 +164,9 @@ static const struct soc_gpio_map gpn_gpio_map[] = {
GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */
GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA),
/* 17 GPIO_SUS3 */
GPI(trig_edge_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA),
GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA),
/* 18 GPIO_SUS7 */
GPI(trig_edge_low, L3, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA),
GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA),
/* 19 GPIO_SUS1 */
GPIO_NC, /* 20 GPIO_SUS5 */
GPIO_NC, /* 21 SEC_GPIO_SUS11 */

4
src/mainboard/google/cyan/variants/setzer/gpio.c
View File

@ -162,9 +162,9 @@ static const struct soc_gpio_map gpn_gpio_map[] = {
GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */
GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA),
/* 17 GPIO_SUS3 */
GPI(trig_edge_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA),
GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA),
/* 18 GPIO_SUS7 */
GPI(trig_edge_low, L3, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA),
GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA),
/* 19 GPIO_SUS1 */
GPIO_NC, /* 20 GPIO_SUS5 */
GPIO_NC, /* 21 SEC_GPIO_SUS11 */

2
src/mainboard/google/cyan/variants/terra/gpio.c
View File

@ -160,7 +160,7 @@ static const struct soc_gpio_map gpn_gpio_map[] = {
GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */
GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA),
/* 17 GPIO_SUS3 */
GPI(trig_edge_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA),
GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA),
/* 18 GPIO_SUS7 */
GPIO_NC, /* 19 GPIO_SUS1 */
GPIO_NC, /* 20 GPIO_SUS5 */

4
src/mainboard/google/cyan/variants/ultima/gpio.c
View File

@ -163,9 +163,9 @@ static const struct soc_gpio_map gpn_gpio_map[] = {
GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */
GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA),
/* 17 GPIO_SUS3 */
GPI(trig_edge_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA),
GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA),
/* 18 GPIO_SUS7 */
GPI(trig_edge_low, L3, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA),
GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA),
/* 19 GPIO_SUS1 */
GPIO_NC, /* 20 GPIO_SUS5 */
GPIO_NC, /* 21 SEC_GPIO_SUS11 */

4
src/mainboard/google/cyan/variants/wizpig/gpio.c
View File

@ -162,9 +162,9 @@ static const struct soc_gpio_map gpn_gpio_map[] = {
GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */
GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA),
/* 17 GPIO_SUS3 */
GPI(trig_edge_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA),
GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA),
/* 18 GPIO_SUS7 */
GPI(trig_edge_low, L3, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA),
GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA),
/* 19 GPIO_SUS1 */
GPIO_NC, /* 20 GPIO_SUS5 */
GPIO_INPUT_NO_PULL, /* 21 SEC_GPIO_SUS11 */

9
src/soc/intel/braswell/include/soc/gpio.h
View File

@ -524,10 +524,11 @@ typedef enum {
typedef enum {
INT_DIS = 0,
trig_edge_low = 1,
trig_edge_high = 2,
trig_edge_both = 3,
trig_level = 4,
trig_edge_low = PAD_TRIG_EDGE_LOW,
trig_edge_high = PAD_TRIG_EDGE_HIGH,
trig_edge_both = PAD_TRIG_EDGE_BOTH,
trig_level_high = PAD_TRIG_EDGE_LEVEL | (0 << 4),
trig_level_low = PAD_TRIG_EDGE_LEVEL | (4 << 4),
} int_type_t;
typedef enum {