winbond/w83627dhg: Add ACPI support
This is loosely based on Christoph Grenz' ACPI code for the W83627HF and makes use of the PnP super i/o ACPI framework. Change-Id: I5e1cd09b83c0041f440562d2a1b73e4560589cb7 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/3288 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Nico Huber
Stefan Reinauer
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Christoph Grenz <christophg+cb@grenz-bonn.de>
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* Copyright (C) 2013 secunet Security Networks AG
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/*
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* Include this file into a mainboard's DSDT _SB device tree and it will
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* expose the W83627DHG SuperIO and some of its functionality.
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*
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* It allows the change of IO ports, IRQs and DMA settings on logical
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* devices, disabling and reenabling logical devices and controlling power
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* saving mode on logical devices or the whole chip.
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*
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* LDN State
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* 0x0 FDC Not implemented
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* 0x1 PP Not implemented
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* 0x2 UARTA Implemented, partially tested
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* 0x3 UARTB UART only, partially tested
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* 0x5 KBC Implemented, untested
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* 0x6 SPI Not implemented
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* 0x7 GPIO6 Not implemented
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* 0x8 WDT0&PLED Not implemented
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* 0x9 GPIO2-5 Not implemented
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* 0xa ACPI Not implemented
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* 0xb HWM Resources, PM only
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* 0xc PECI&SST Not implemented
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*
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* Controllable through preprocessor defines:
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* SUPERIO_DEV Device identifier for this SIO (e.g. SIO0)
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* SUPERIO_PNP_BASE I/o address of the first PnP configuration register
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* W83627DHG_SHOW_UARTA If defined, UARTA will be exposed.
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* W83627DHG_SHOW_UARTB If defined, UARTB will be exposed.
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* W83627DHG_SHOW_KBC If defined, the KBC will be exposed.
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* W83627DHG_SHOW_PS2M If defined, PS/2 mouse support will be exposed.
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* W83627DHG_SHOW_HWMON If defined, the hardware monitor will be exposed.
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*/
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#undef SUPERIO_CHIP_NAME
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#define SUPERIO_CHIP_NAME W83627DHG
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#include <superio/acpi/pnp.asl>
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Device(SUPERIO_DEV) {
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Name (_HID, EisaId("PNP0A05"))
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Name (_STR, Unicode("Winbond W83627DHG Super I/O"))
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Name (_UID, SUPERIO_UID(SUPERIO_DEV,))
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/* Mutex for accesses to the configuration ports */
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Mutex(CRMX, 1)
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/* SuperIO configuration ports */
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OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 0x02)
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Field (CREG, ByteAcc, NoLock, Preserve)
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{
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PNP_ADDR_REG, 8,
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PNP_DATA_REG, 8
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}
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IndexField (ADDR, DATA, ByteAcc, NoLock, Preserve)
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{
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Offset (0x07),
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PNP_LOGICAL_DEVICE, 8, /* Logical device selector */
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Offset (0x22),
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FDPW, 1, /* FDC Power Down */
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, 2,
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PRPW, 1, /* PRT Power Down */
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UAPW, 1, /* UART A Power Down */
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UBPW, 1, /* UART B Power Down */
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HWPW, 1, /* HWM Power Down */
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Offset (0x23),
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IPD, 1, /* Immediate Chip Power Down */
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Offset (0x30),
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PNP_DEVICE_ACTIVE, 1, /* Logical device activation */
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Offset (0x60),
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PNP_IO0_HIGH_BYTE, 8, /* First I/O port base - high byte */
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PNP_IO0_LOW_BYTE, 8, /* First I/O port base - low byte */
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Offset (0x62),
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PNP_IO1_HIGH_BYTE, 8, /* Second I/O port base - high byte */
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PNP_IO1_LOW_BYTE, 8, /* Second I/O port base - low byte */
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Offset (0x70),
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PNP_IRQ0, 8, /* First IRQ */
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Offset (0x72),
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PNP_IRQ1, 8, /* Second IRQ */
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Offset (0x74),
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PNP_DMA0, 8, /* DMA */
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}
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Method (_CRS)
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{
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/* Announce the used i/o ports to the OS */
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Return (ResourceTemplate () {
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IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE, 0x01, 0x02)
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})
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}
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#undef PNP_ENTER_MAGIC_1ST
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#undef PNP_ENTER_MAGIC_2ND
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#undef PNP_ENTER_MAGIC_3RD
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#undef PNP_EXIT_MAGIC_1ST
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#define PNP_ENTER_MAGIC_1ST 0x87
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#define PNP_ENTER_MAGIC_2ND 0x87
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#define PNP_EXIT_MAGIC_1ST 0xaa
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#include <superio/acpi/pnp_config.asl>
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/* PM: indicate IPD (Immediate Power Down) bit state as D0/D2 */
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Method (_PSC) {
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ENTER_CONFIG_MODE (PNP_NO_LDN_CHANGE)
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Store (IPD, Local0)
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EXIT_CONFIG_MODE ()
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If (Local0) { Return (2) }
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Else { Return (0) }
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}
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/* PM: Switch to D0 by setting IPD low */
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Method (_PS0) {
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ENTER_CONFIG_MODE (PNP_NO_LDN_CHANGE)
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Store (Zero, IPD)
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EXIT_CONFIG_MODE ()
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}
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/* PM: Switch to D2 by setting IPD high */
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Method (_PS2) {
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ENTER_CONFIG_MODE (PNP_NO_LDN_CHANGE)
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Store (One, IPD)
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EXIT_CONFIG_MODE ()
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}
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#ifdef W83627DHG_SHOW_UARTA
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#undef SUPERIO_UART_LDN
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#undef SUPERIO_UART_DDN
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#undef SUPERIO_UART_PM_REG
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#undef SUPERIO_UART_PM_LDN
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#define SUPERIO_UART_LDN 2
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#define SUPERIO_UART_PM_REG UAPW
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#define SUPERIO_UART_PM_LDN PNP_NO_LDN_CHANGE
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#include <superio/acpi/pnp_uart.asl>
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#endif
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#ifdef W83627DHG_SHOW_UARTB
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#undef SUPERIO_UART_LDN
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#undef SUPERIO_UART_DDN
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#undef SUPERIO_UART_PM_REG
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#undef SUPERIO_UART_PM_LDN
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#define SUPERIO_UART_LDN 3
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#define SUPERIO_UART_PM_REG UBPW
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#define SUPERIO_UART_PM_LDN PNP_NO_LDN_CHANGE
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#include <superio/acpi/pnp_uart.asl>
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#endif
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#ifdef W83627DHG_SHOW_KBC
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#undef SUPERIO_KBC_LDN
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#undef SUPERIO_KBC_PS2M
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#undef SUPERIO_KBC_PS2LDN
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#define SUPERIO_KBC_LDN 5
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#ifdef W83627DHG_SHOW_PS2M
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#define SUPERIO_KBC_PS2M 1
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#endif
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#include <superio/acpi/pnp_kbc.asl>
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#endif
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#ifdef W83627DHG_SHOW_HWMON
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#undef SUPERIO_PNP_LDN
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#undef SUPERIO_PNP_DDN
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#undef SUPERIO_PNP_PM_REG
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#undef SUPERIO_PNP_PM_LDN
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#undef SUPERIO_PNP_IO0
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#undef SUPERIO_PNP_IO1
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#undef SUPERIO_PNP_IRQ0
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#undef SUPERIO_PNP_IRQ1
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#undef SUPERIO_PNP_DMA
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#define SUPERIO_PNP_LDN 11
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#define SUPERIO_PNP_PM_REG HWPW
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#define SUPERIO_PNP_PM_LDN PNP_NO_LDN_CHANGE
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#define SUPERIO_PNP_IO0 0x08, 0x08
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#define SUPERIO_PNP_IRQ0 1
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#include <superio/acpi/pnp_generic.asl>
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#endif
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}
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