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soc/intel/common: Add function to get soc reserved memory size 

This patch ensures to consider soc reserved memory size while
allocating DRAM based resources.

Change-Id: I587a9c1ea44f2dbf67099fef03d0ff92bc44f242
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Subrata Banik 2017-09-17 21:16:22 +05:30 committed by Aaron Durbin
parent 7387e04a35
commit 73b8503183
2 changed files with 18 additions and 4 deletions
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4
src/soc/intel/common/block/include/intelblocks/systemagent.h
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@ -103,4 +103,8 @@ void soc_add_fixed_mmio_resources(struct device *dev, int *resource_cnt);
/* SoC specific APIs to get UNCORE PRMRR base and mask values /* SoC specific APIs to get UNCORE PRMRR base and mask values
* returns 0, if able to get base and mask values; otherwise returns -1 */ * returns 0, if able to get base and mask values; otherwise returns -1 */
int soc_get_uncore_prmmr_base_and_mask(uint64_t *base, uint64_t *mask); int soc_get_uncore_prmmr_base_and_mask(uint64_t *base, uint64_t *mask);
/* SoC call to summarize all Intel Reserve MMIO size and report to SA */
size_t soc_reserved_mmio_size(void);
#endif /* SOC_INTEL_COMMON_BLOCK_SA_H */ #endif /* SOC_INTEL_COMMON_BLOCK_SA_H */

18
src/soc/intel/common/block/systemagent/systemagent.c
View File

@ -43,6 +43,11 @@ __attribute__((weak)) int soc_get_uncore_prmmr_base_and_mask(uint64_t *base,
return -1; return -1;
} }
__attribute__((weak)) size_t soc_reserved_mmio_size(void)
{
return 0;
}
/* /*
* Add all known fixed MMIO ranges that hang off the host bridge/memory * Add all known fixed MMIO ranges that hang off the host bridge/memory
* controller device. * controller device.
@ -141,6 +146,7 @@ static void sa_add_dram_resources(struct device *dev, int *resource_count)
{ {
uintptr_t base_k, touud_k; uintptr_t base_k, touud_k;
size_t dpr_size = 0, size_k; size_t dpr_size = 0, size_k;
size_t reserved_mmio_size;
uint64_t sa_map_values[MAX_MAP_ENTRIES]; uint64_t sa_map_values[MAX_MAP_ENTRIES];
uintptr_t top_of_ram; uintptr_t top_of_ram;
int index = *resource_count; int index = *resource_count;
@ -148,6 +154,9 @@ static void sa_add_dram_resources(struct device *dev, int *resource_count)
if (IS_ENABLED(CONFIG_SA_ENABLE_DPR)) if (IS_ENABLED(CONFIG_SA_ENABLE_DPR))
dpr_size = sa_get_dpr_size(); dpr_size = sa_get_dpr_size();
/* Get SoC reserve memory size as per user selection */
reserved_mmio_size = soc_reserved_mmio_size();
top_of_ram = (uintptr_t)cbmem_top(); top_of_ram = (uintptr_t)cbmem_top();
/* 0 - > 0xa0000 */ /* 0 - > 0xa0000 */
@ -162,13 +171,14 @@ static void sa_add_dram_resources(struct device *dev, int *resource_count)
sa_get_mem_map(dev, &sa_map_values[0]); sa_get_mem_map(dev, &sa_map_values[0]);
/* top_of_ram -> TSEG - DPR */ /* top_of_ram -> TSEG - DPR - Intel Reserve Memory Size*/
base_k = top_of_ram; base_k = top_of_ram;
size_k = sa_map_values[SA_TSEG_REG] - dpr_size - base_k; size_k = sa_map_values[SA_TSEG_REG] - dpr_size - base_k
- reserved_mmio_size;
mmio_resource(dev, index++, base_k / KiB, size_k / KiB); mmio_resource(dev, index++, base_k / KiB, size_k / KiB);
/* TSEG - DPR -> BGSM */ /* TSEG - DPR - Intel Reserve Memory Size -> BGSM */
base_k = sa_map_values[SA_TSEG_REG] - dpr_size; base_k = sa_map_values[SA_TSEG_REG] - dpr_size - reserved_mmio_size;
size_k = sa_map_values[SA_BGSM_REG] - base_k; size_k = sa_map_values[SA_BGSM_REG] - base_k;
reserved_ram_resource(dev, index++, base_k / KiB, size_k / KiB); reserved_ram_resource(dev, index++, base_k / KiB, size_k / KiB);