fsp_broadwell_de: Switch to common SPI controller driver
The common SPI controller driver in src/southbridge/intel/common does match the SPI controller included in the PCH of Broadwell-DE SoC. Switch to the usage of this driver and delete the dedicated one for the FSP based Broadwell-DE implementation. TEST: Boot mc_bdx1 with SPI driver active in romstage Change-Id: I4fe8057ea1981e350659a5caa9912fb758110115 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/29633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Werner Zeh
Patrick Georgi
parent
a0f29312b4
commit
73bbcee932
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@ -12,12 +12,13 @@ config CPU_SPECIFIC_OPTIONS
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select ARCH_VERSTAGE_X86_32
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select ARCH_ROMSTAGE_X86_32
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select ARCH_RAMSTAGE_X86_32
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select SOUTHBRIDGE_INTEL_COMMON
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select SOUTHBRIDGE_INTEL_COMMON_SPI
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select SOUTHBRIDGE_INTEL_COMMON_RESET
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select NO_RELOCATABLE_RAMSTAGE
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select PARALLEL_MP
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select SMP
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select IOAPIC
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select SPI_FLASH
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select UDELAY_TSC
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select SUPPORT_CPU_UCODE_IN_CBFS
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# Microcode header files are delivered in FSP package
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@ -12,9 +12,6 @@ subdirs-y += ../../../lib/fsp
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subdirs-y += fsp
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romstage-y += gpio.c
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romstage-y += spi.c
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ramstage-y += spi.c
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ramstage-y += cpu.c
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ramstage-y += chip.c
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ramstage-y += northcluster.c
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@ -1,626 +0,0 @@
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/*
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* Copyright (c) 2013 Google Inc.
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* Copyright (C) 2015-2016 Intel Corp.
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* Copyright (C) 2016 Siemens AG
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but without any warranty; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* This file is derived from the flashrom project. */
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#include <stdint.h>
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#include <stdlib.h>
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#include <string.h>
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#include <delay.h>
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#include <commonlib/helpers.h>
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#include <arch/io.h>
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#include <console/console.h>
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#include <device/pci_ids.h>
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#include <spi_flash.h>
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#include <spi-generic.h>
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#include <arch/early_variables.h>
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#ifdef __SMM__
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#define pci_read_config_byte(dev, reg, targ)\
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*(targ) = pci_read_config8(dev, reg)
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#define pci_read_config_word(dev, reg, targ)\
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*(targ) = pci_read_config16(dev, reg)
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#define pci_read_config_dword(dev, reg, targ)\
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*(targ) = pci_read_config32(dev, reg)
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#define pci_write_config_byte(dev, reg, val)\
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pci_write_config8(dev, reg, val)
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#define pci_write_config_word(dev, reg, val)\
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pci_write_config16(dev, reg, val)
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#define pci_write_config_dword(dev, reg, val)\
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pci_write_config32(dev, reg, val)
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#else /* !__SMM__ */
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#include <device/device.h>
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#include <device/pci.h>
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#define pci_read_config_byte(dev, reg, targ)\
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*(targ) = pci_read_config8(dev, reg)
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#define pci_read_config_word(dev, reg, targ)\
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*(targ) = pci_read_config16(dev, reg)
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#define pci_read_config_dword(dev, reg, targ)\
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*(targ) = pci_read_config32(dev, reg)
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#define pci_write_config_byte(dev, reg, val)\
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pci_write_config8(dev, reg, val)
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#define pci_write_config_word(dev, reg, val)\
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pci_write_config16(dev, reg, val)
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#define pci_write_config_dword(dev, reg, val)\
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pci_write_config32(dev, reg, val)
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#endif /* !__SMM__ */
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typedef struct spi_slave ich_spi_slave;
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static int ichspi_lock CAR_GLOBAL = 0;
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typedef struct ich9_spi_regs {
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uint32_t bfpr;
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uint16_t hsfs;
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uint16_t hsfc;
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uint32_t faddr;
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uint32_t _reserved0;
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uint32_t fdata[16];
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uint32_t frap;
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uint32_t freg[5];
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uint32_t _reserved1[3];
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uint32_t pr[5];
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uint32_t _reserved2[2];
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uint8_t ssfs;
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uint8_t ssfc[3];
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uint16_t preop;
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uint16_t optype;
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uint8_t opmenu[8];
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uint32_t bbar;
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uint8_t _reserved3[12];
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uint32_t fdoc;
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uint32_t fdod;
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uint8_t _reserved4[8];
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uint32_t afc;
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uint32_t lvscc;
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uint32_t uvscc;
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uint8_t _reserved5[4];
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uint32_t fpb;
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uint8_t _reserved6[28];
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uint32_t srdl;
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uint32_t srdc;
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uint32_t srd;
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} __packed ich9_spi_regs;
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typedef struct ich_spi_controller {
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int locked;
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uint8_t *opmenu;
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int menubytes;
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uint16_t *preop;
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uint16_t *optype;
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uint32_t *addr;
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uint8_t *data;
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unsigned databytes;
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uint8_t *status;
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uint16_t *control;
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uint32_t *bbar;
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} ich_spi_controller;
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static ich_spi_controller cntlr CAR_GLOBAL;
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enum {
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SPIS_SCIP = 0x0001,
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SPIS_GRANT = 0x0002,
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SPIS_CDS = 0x0004,
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SPIS_FCERR = 0x0008,
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SSFS_AEL = 0x0010,
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SPIS_LOCK = 0x8000,
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SPIS_RESERVED_MASK = 0x7ff0,
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SSFS_RESERVED_MASK = 0x7fe2
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};
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enum {
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SPIC_SCGO = 0x000002,
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SPIC_ACS = 0x000004,
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SPIC_SPOP = 0x000008,
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SPIC_DBC = 0x003f00,
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SPIC_DS = 0x004000,
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SPIC_SME = 0x008000,
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SSFC_SCF_MASK = 0x070000,
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SSFC_RESERVED = 0xf80000
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};
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enum {
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HSFS_FDONE = 0x0001,
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HSFS_FCERR = 0x0002,
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HSFS_AEL = 0x0004,
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HSFS_BERASE_MASK = 0x0018,
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HSFS_BERASE_SHIFT = 3,
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HSFS_SCIP = 0x0020,
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HSFS_FDOPSS = 0x2000,
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HSFS_FDV = 0x4000,
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HSFS_FLOCKDN = 0x8000
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};
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enum {
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HSFC_FGO = 0x0001,
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HSFC_FCYCLE_MASK = 0x0006,
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HSFC_FCYCLE_SHIFT = 1,
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HSFC_FDBC_MASK = 0x3f00,
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HSFC_FDBC_SHIFT = 8,
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HSFC_FSMIE = 0x8000
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};
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enum {
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SPI_OPCODE_TYPE_READ_NO_ADDRESS = 0,
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SPI_OPCODE_TYPE_WRITE_NO_ADDRESS = 1,
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SPI_OPCODE_TYPE_READ_WITH_ADDRESS = 2,
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SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3
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};
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#define SPI_OFFSET_MASK 0x3ff
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static uint8_t readb_(const void *addr)
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{
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uint8_t v = read8(addr);
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if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) {
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printk(BIOS_DEBUG, "SPI: read %2.2x from %4.4x\n",
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v, ((uint32_t) addr) & SPI_OFFSET_MASK);
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}
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return v;
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}
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static uint16_t readw_(const void *addr)
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{
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uint16_t v = read16(addr);
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if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) {
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printk(BIOS_DEBUG, "SPI: read %4.4x from %4.4x\n",
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v, ((uint32_t) addr) & SPI_OFFSET_MASK);
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}
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return v;
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}
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static uint32_t readl_(const void *addr)
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{
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uint32_t v = read32(addr);
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if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) {
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printk(BIOS_DEBUG, "SPI: read %8.8x from %4.4x\n",
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v, ((uint32_t) addr) & SPI_OFFSET_MASK);
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}
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return v;
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}
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static void writeb_(uint8_t b, void *addr)
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{
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write8(addr, b);
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if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) {
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printk(BIOS_DEBUG, "SPI: wrote %2.2x to %4.4x\n",
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b, ((uint32_t) addr) & SPI_OFFSET_MASK);
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}
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}
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static void writew_(uint16_t b, void *addr)
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{
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write16(addr, b);
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if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) {
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printk(BIOS_DEBUG, "SPI: wrote %4.4x to %4.4x\n",
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b, ((uint32_t) addr) & SPI_OFFSET_MASK);
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}
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}
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static void writel_(uint32_t b, void *addr)
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{
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write32(addr, b);
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if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) {
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printk(BIOS_DEBUG, "SPI: wrote %8.8x to %4.4x\n",
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b, ((uint32_t) addr) & SPI_OFFSET_MASK);
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}
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}
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static void write_reg(const void *value, void *dest, uint32_t size)
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{
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const uint8_t *bvalue = value;
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uint8_t *bdest = dest;
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while (size >= 4) {
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writel_(*(const uint32_t *)bvalue, bdest);
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bdest += 4; bvalue += 4; size -= 4;
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}
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while (size) {
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writeb_(*bvalue, bdest);
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bdest++; bvalue++; size--;
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}
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}
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static void read_reg(const void *src, void *value, uint32_t size)
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{
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const uint8_t *bsrc = src;
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uint8_t *bvalue = value;
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while (size >= 4) {
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*(uint32_t *)bvalue = readl_(bsrc);
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bsrc += 4; bvalue += 4; size -= 4;
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}
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while (size) {
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*bvalue = readb_(bsrc);
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bsrc++; bvalue++; size--;
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}
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}
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static void ich_set_bbar(uint32_t minaddr)
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{
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const uint32_t bbar_mask = 0x00ffff00;
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uint32_t ichspi_bbar;
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minaddr &= bbar_mask;
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ichspi_bbar = readl_(cntlr.bbar) & ~bbar_mask;
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ichspi_bbar |= minaddr;
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writel_(ichspi_bbar, cntlr.bbar);
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}
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void spi_init(void)
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{
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uint8_t *rcrb; /* Root Complex Register Block */
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uint32_t rcba; /* Root Complex Base Address */
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uint8_t bios_cntl;
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ich9_spi_regs *ich9_spi;
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#if defined(__SIMPLE_DEVICE__)
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pci_devfn_t dev = PCI_DEV(0, 31, 0);
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#else
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struct device *dev;
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dev = dev_find_slot(0, PCI_DEVFN(31, 0));
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#endif
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pci_read_config_dword(dev, 0xf0, &rcba);
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/* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */
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rcrb = (uint8_t *)(rcba & 0xffffc000);
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ich9_spi = (ich9_spi_regs *)(rcrb + 0x3800);
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ichspi_lock = readw_(&ich9_spi->hsfs) & HSFS_FLOCKDN;
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cntlr.opmenu = ich9_spi->opmenu;
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cntlr.menubytes = sizeof(ich9_spi->opmenu);
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cntlr.optype = &ich9_spi->optype;
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cntlr.addr = &ich9_spi->faddr;
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cntlr.data = (uint8_t *)ich9_spi->fdata;
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cntlr.databytes = sizeof(ich9_spi->fdata);
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cntlr.status = &ich9_spi->ssfs;
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cntlr.control = (uint16_t *)ich9_spi->ssfc;
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cntlr.bbar = &ich9_spi->bbar;
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cntlr.preop = &ich9_spi->preop;
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ich_set_bbar(0);
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/* Disable the BIOS write protect so write commands are allowed. */
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pci_read_config_byte(dev, 0xdc, &bios_cntl);
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bios_cntl &= ~(1 << 5);
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pci_write_config_byte(dev, 0xdc, bios_cntl | 0x1);
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}
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typedef struct spi_transaction {
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const uint8_t *out;
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uint32_t bytesout;
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uint8_t *in;
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uint32_t bytesin;
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uint8_t type;
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uint8_t opcode;
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uint32_t offset;
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} spi_transaction;
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static inline void spi_use_out(spi_transaction *trans, unsigned bytes)
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{
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trans->out += bytes;
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trans->bytesout -= bytes;
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}
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static inline void spi_use_in(spi_transaction *trans, unsigned bytes)
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{
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trans->in += bytes;
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trans->bytesin -= bytes;
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}
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static void spi_setup_type(spi_transaction *trans)
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{
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trans->type = 0xFF;
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/* Try to guess spi type from read/write sizes. */
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if (trans->bytesin == 0) {
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if (trans->bytesout > 4)
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/*
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* If bytesin = 0 and bytesout > 4, we presume this is
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* a write data operation, which is accompanied by an
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* address.
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*/
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trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS;
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else
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trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS;
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return;
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}
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if (trans->bytesout == 1) { /* and bytesin is > 0 */
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trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS;
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return;
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}
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if (trans->bytesout == 4) { /* and bytesin is > 0 */
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trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
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}
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/* Fast read command is called with 5 bytes instead of 4 */
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if (trans->out[0] == SPI_OPCODE_FAST_READ && trans->bytesout == 5) {
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trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
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--trans->bytesout;
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}
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}
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static int spi_setup_opcode(spi_transaction *trans)
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{
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uint16_t optypes;
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uint8_t opmenu[cntlr.menubytes];
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trans->opcode = trans->out[0];
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spi_use_out(trans, 1);
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if (!ichspi_lock) {
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/* The lock is off, so just use index 0. */
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writeb_(trans->opcode, cntlr.opmenu);
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optypes = readw_(cntlr.optype);
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optypes = (optypes & 0xfffc) | (trans->type & 0x3);
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writew_(optypes, cntlr.optype);
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return 0;
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} else {
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/* The lock is on. See if what we need is on the menu. */
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uint8_t optype;
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uint16_t opcode_index;
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/* Write Enable is handled as atomic prefix */
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if (trans->opcode == SPI_OPCODE_WREN)
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return 0;
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read_reg(cntlr.opmenu, opmenu, sizeof(opmenu));
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for (opcode_index = 0; opcode_index < cntlr.menubytes;
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opcode_index++) {
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if (opmenu[opcode_index] == trans->opcode)
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break;
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}
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if (opcode_index == cntlr.menubytes) {
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printk(BIOS_DEBUG, "ICH SPI: Opcode %x not found\n",
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trans->opcode);
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return -1;
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}
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optypes = readw_(cntlr.optype);
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optype = (optypes >> (opcode_index * 2)) & 0x3;
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if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS &&
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optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS &&
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trans->bytesout >= 3) {
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/* We guessed wrong earlier. Fix it up. */
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trans->type = optype;
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}
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if (optype != trans->type) {
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printk(BIOS_DEBUG, "ICH SPI: Transaction doesn't fit type %d\n",
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optype);
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return -1;
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}
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return opcode_index;
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}
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}
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static int spi_setup_offset(spi_transaction *trans)
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{
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/* Separate the SPI address and data. */
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switch (trans->type) {
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case SPI_OPCODE_TYPE_READ_NO_ADDRESS:
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case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS:
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return 0;
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case SPI_OPCODE_TYPE_READ_WITH_ADDRESS:
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case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS:
|
||||
trans->offset = ((uint32_t)trans->out[0] << 16) |
|
||||
((uint32_t)trans->out[1] << 8) |
|
||||
((uint32_t)trans->out[2] << 0);
|
||||
spi_use_out(trans, 3);
|
||||
return 1;
|
||||
default:
|
||||
printk(BIOS_DEBUG, "Unrecognized SPI transaction type %#x\n", trans->type);
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Wait for up to 60ms til status register bit(s) turn 1 (in case wait_til_set
|
||||
* below is True) or 0. In case the wait was for the bit(s) to set - write
|
||||
* those bits back, which would cause resetting them.
|
||||
*
|
||||
* Return the last read status value on success or -1 on failure.
|
||||
*/
|
||||
static int ich_status_poll(uint16_t bitmask, int wait_til_set)
|
||||
{
|
||||
int timeout = 40000; /* This will result in 400 ms */
|
||||
uint16_t status = 0;
|
||||
|
||||
while (timeout--) {
|
||||
status = readw_(cntlr.status);
|
||||
if (wait_til_set ^ ((status & bitmask) == 0)) {
|
||||
if (wait_til_set)
|
||||
writew_((status & bitmask), cntlr.status);
|
||||
return status;
|
||||
}
|
||||
udelay(10);
|
||||
}
|
||||
|
||||
printk(BIOS_DEBUG, "ICH SPI: SCIP timeout, read %x, expected %x\n",
|
||||
status, bitmask);
|
||||
return -1;
|
||||
}
|
||||
|
||||
static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout,
|
||||
size_t bytesout, void *din, size_t bytesin)
|
||||
{
|
||||
uint16_t control;
|
||||
int16_t opcode_index;
|
||||
int with_address;
|
||||
int status;
|
||||
|
||||
spi_transaction trans = {
|
||||
dout, bytesout,
|
||||
din, bytesin,
|
||||
0xff, 0xff, 0
|
||||
};
|
||||
|
||||
/* There has to always at least be an opcode. */
|
||||
if (!bytesout || !dout) {
|
||||
printk(BIOS_DEBUG, "ICH SPI: No opcode for transfer\n");
|
||||
return -1;
|
||||
}
|
||||
/* Make sure if we read something we have a place to put it. */
|
||||
if (bytesin != 0 && !din) {
|
||||
printk(BIOS_DEBUG, "ICH SPI: Read but no target buffer\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (ich_status_poll(SPIS_SCIP, 0) == -1)
|
||||
return -1;
|
||||
|
||||
writew_(SPIS_CDS | SPIS_FCERR, cntlr.status);
|
||||
|
||||
spi_setup_type(&trans);
|
||||
opcode_index = spi_setup_opcode(&trans);
|
||||
if (opcode_index < 0)
|
||||
return -1;
|
||||
with_address = spi_setup_offset(&trans);
|
||||
if (with_address < 0)
|
||||
return -1;
|
||||
|
||||
if (!ichspi_lock && trans.opcode == SPI_OPCODE_WREN) {
|
||||
/*
|
||||
* Treat Write Enable as Atomic Pre-Op if possible
|
||||
* in order to prevent the Management Engine from
|
||||
* issuing a transaction between WREN and DATA.
|
||||
*/
|
||||
writew_(trans.opcode, cntlr.preop);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Preset control fields */
|
||||
control = SPIC_SCGO | ((opcode_index & 0x07) << 4);
|
||||
|
||||
/* Issue atomic preop cycle if needed */
|
||||
if (readw_(cntlr.preop))
|
||||
control |= SPIC_ACS;
|
||||
|
||||
if (!trans.bytesout && !trans.bytesin) {
|
||||
/* SPI addresses are 24 bit only */
|
||||
if (with_address)
|
||||
writel_(trans.offset & 0x00FFFFFF, cntlr.addr);
|
||||
|
||||
/*
|
||||
* This is a 'no data' command (like Write Enable), its
|
||||
* bitesout size was 1, decremented to zero while executing
|
||||
* spi_setup_opcode() above. Tell the chip to send the
|
||||
* command.
|
||||
*/
|
||||
writew_(control, cntlr.control);
|
||||
|
||||
/* wait for the result */
|
||||
status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1);
|
||||
if (status == -1)
|
||||
return -1;
|
||||
|
||||
if (status & SPIS_FCERR) {
|
||||
printk(BIOS_DEBUG, "ICH SPI: Command transaction error\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
goto spi_xfer_exit;
|
||||
}
|
||||
|
||||
/*
|
||||
* Check if this is a write command attempting to transfer more bytes
|
||||
* than the controller can handle. Iterations for writes are not
|
||||
* supported here because each SPI write command needs to be preceded
|
||||
* and followed by other SPI commands, and this sequence is controlled
|
||||
* by the SPI chip driver.
|
||||
*/
|
||||
if (trans.bytesout > cntlr.databytes) {
|
||||
printk(BIOS_DEBUG, "ICH SPI: Too much to write. Does your SPI chip driver use"
|
||||
" spi_crop_chunk()?\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
/*
|
||||
* Read or write up to databytes bytes at a time until everything has
|
||||
* been sent.
|
||||
*/
|
||||
while (trans.bytesout || trans.bytesin) {
|
||||
uint32_t data_length;
|
||||
|
||||
/* SPI addresses are 24 bit only */
|
||||
writel_(trans.offset & 0x00FFFFFF, cntlr.addr);
|
||||
|
||||
if (trans.bytesout)
|
||||
data_length = min(trans.bytesout, cntlr.databytes);
|
||||
else
|
||||
data_length = min(trans.bytesin, cntlr.databytes);
|
||||
|
||||
/* Program data into FDATA0 to N */
|
||||
if (trans.bytesout) {
|
||||
write_reg(trans.out, cntlr.data, data_length);
|
||||
spi_use_out(&trans, data_length);
|
||||
if (with_address)
|
||||
trans.offset += data_length;
|
||||
}
|
||||
|
||||
/* Add proper control fields' values */
|
||||
control &= ~((cntlr.databytes - 1) << 8);
|
||||
control |= SPIC_DS;
|
||||
control |= (data_length - 1) << 8;
|
||||
|
||||
/* write it */
|
||||
writew_(control, cntlr.control);
|
||||
|
||||
/* Wait for Cycle Done Status or Flash Cycle Error. */
|
||||
status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1);
|
||||
if (status == -1)
|
||||
return -1;
|
||||
|
||||
if (status & SPIS_FCERR) {
|
||||
printk(BIOS_DEBUG, "ICH SPI: Data transaction error\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (trans.bytesin) {
|
||||
read_reg(cntlr.data, trans.in, data_length);
|
||||
spi_use_in(&trans, data_length);
|
||||
if (with_address)
|
||||
trans.offset += data_length;
|
||||
}
|
||||
}
|
||||
|
||||
spi_xfer_exit:
|
||||
/* Clear atomic preop now that xfer is done */
|
||||
writew_(0, cntlr.preop);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int xfer_vectors(const struct spi_slave *slave,
|
||||
struct spi_op vectors[], size_t count)
|
||||
{
|
||||
return spi_flash_vector_helper(slave, vectors, count, spi_ctrlr_xfer);
|
||||
}
|
||||
|
||||
static const struct spi_ctrlr spi_ctrlr = {
|
||||
.xfer_vector = xfer_vectors,
|
||||
.max_xfer_size = member_size(ich9_spi_regs, fdata),
|
||||
};
|
||||
|
||||
const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
|
||||
{
|
||||
.ctrlr = &spi_ctrlr,
|
||||
.bus_start = 0,
|
||||
.bus_end = 0,
|
||||
},
|
||||
};
|
||||
|
||||
const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map);
|
||||
Loading…
Reference in New Issue