From 73c0a05bc704659fcd1c70cc5d97e134de54c8f3 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Fri, 13 Dec 2013 16:01:56 -0800 Subject: [PATCH] rambi: Disable HSUART2 and SPI interfaces MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Not used currently on rambi board. Disable in case it saves power. BUG=chrome-os-partner:23862 BRANCH=none TEST=build and boot on rambi Change-Id: Idb870c2cfa88cb6c3f1ada3caf0db566e33ec1eb Signed-off-by: Duncan Laurie Reviewed-on: https://chromium-review.googlesource.com/180084 Reviewed-by: Aaron Durbin Signed-off-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/5020 Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/mainboard/google/rambi/devicetree.cb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/rambi/devicetree.cb b/src/mainboard/google/rambi/devicetree.cb index bfb9e303e1..fe5ec7b46a 100644 --- a/src/mainboard/google/rambi/devicetree.cb +++ b/src/mainboard/google/rambi/devicetree.cb @@ -75,8 +75,8 @@ chip soc/intel/baytrail device pci 1e.1 off end # PWM1 device pci 1e.2 off end # PWM2 device pci 1e.3 off end # HSUART1 - device pci 1e.4 on end # HSUART2 - device pci 1e.5 on end # SPI + device pci 1e.4 off end # HSUART2 + device pci 1e.5 off end # SPI device pci 1f.0 on chip ec/google/chromeec # We only have one init function that