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soc/amd/cezanne: Move APOB update into ramstage 

There is no technical reason this needs to be done in romstage. Moving
it into ramstage allow us (in future CLs) to use threads to pre-load
the apob from SPI.

BUG=b:179699789
TEST=Boot and Ezkinil and Guybrush and verify APOB update still work

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I960437ff4400645de5a3e7447fcdbc52de85943e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This commit is contained in:
Raul E Rangel 2021-07-12 09:21:51 -06:00 committed by Raul Rangel
parent 2c7080692a
commit 73e0f18b35
5 changed files with 4 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/soc/amd/cezanne/romstage.c
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@ -2,7 +2,6 @@
#include <acpi/acpi.h> #include <acpi/acpi.h>
#include <amdblocks/acpimmio.h> #include <amdblocks/acpimmio.h>
#include <amdblocks/apob_cache.h>
#include <amdblocks/memmap.h> #include <amdblocks/memmap.h>
#include <amdblocks/pmlib.h> #include <amdblocks/pmlib.h>
#include <arch/cpu.h> #include <arch/cpu.h>
@ -25,7 +24,6 @@ asmlinkage void car_stage_entry(void)
fill_chipset_state(); fill_chipset_state();
fsp_memory_init(acpi_is_wakeup_s3()); fsp_memory_init(acpi_is_wakeup_s3());
soc_update_apob_cache();
/* Fixup settings FSP-M should not be changing */ /* Fixup settings FSP-M should not be changing */
fch_disable_legacy_dma_io(); fch_disable_legacy_dma_io();

1
src/soc/amd/common/block/apob/Makefile.inc
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@ -1,3 +1,4 @@
ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_APOB),y) ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_APOB),y)
romstage-y += apob_cache.c romstage-y += apob_cache.c
ramstage-y += apob_cache.c
endif # CONFIG_SOC_AMD_COMMON_BLOCK_APOB endif # CONFIG_SOC_AMD_COMMON_BLOCK_APOB

4
src/soc/amd/common/block/apob/apob_cache.c
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@ -4,6 +4,7 @@
#include <amdblocks/apob_cache.h> #include <amdblocks/apob_cache.h>
#include <assert.h> #include <assert.h>
#include <boot_device.h> #include <boot_device.h>
#include <bootstate.h>
#include <commonlib/region.h> #include <commonlib/region.h>
#include <console/console.h> #include <console/console.h>
#include <fmap.h> #include <fmap.h>
@ -96,7 +97,7 @@ static void *get_apob_from_nv_region(struct region *region)
} }
/* Save APOB buffer to flash */ /* Save APOB buffer to flash */
void soc_update_apob_cache(void) static void soc_update_apob_cache(void *unused)
{ {
struct apob_base_header *apob_rom; struct apob_base_header *apob_rom;
struct region_device write_rdev; struct region_device write_rdev;
@ -183,3 +184,4 @@ void *soc_fill_apob_cache(void)
*/ */
return get_apob_nv_address(); return get_apob_nv_address();
} }
BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, soc_update_apob_cache, NULL);

1
src/soc/amd/common/block/include/amdblocks/apob_cache.h
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@ -4,6 +4,5 @@
#define AMD_BLOCK_APOB_CACHE_H #define AMD_BLOCK_APOB_CACHE_H
void *soc_fill_apob_cache(void); void *soc_fill_apob_cache(void);
void soc_update_apob_cache(void);
#endif /* AMD_BLOCK_APOB_CACHE_H */ #endif /* AMD_BLOCK_APOB_CACHE_H */

2
src/soc/amd/picasso/romstage.c
View File

@ -1,7 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h> #include <acpi/acpi.h>
#include <amdblocks/apob_cache.h>
#include <amdblocks/memmap.h> #include <amdblocks/memmap.h>
#include <amdblocks/pmlib.h> #include <amdblocks/pmlib.h>
#include <arch/cpu.h> #include <arch/cpu.h>
@ -27,7 +26,6 @@ asmlinkage void car_stage_entry(void)
post_code(0x43); post_code(0x43);
fsp_memory_init(acpi_is_wakeup_s3()); fsp_memory_init(acpi_is_wakeup_s3());
soc_update_apob_cache();
memmap_stash_early_dram_usage(); memmap_stash_early_dram_usage();