From 73fa035b2053870776c9c81a821b6a1603dc13f1 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 3 Jul 2020 12:29:03 +0200 Subject: [PATCH] nb/intel/haswell: Add `mb_late_romstage_setup` function This function is called at the end of `romstage_common`. Only one board makes use of it, the Lenovo ThinkPad T440p. To preserve behavior, call it after `romstage_common` has done nearly everything. Change-Id: I35742879e737be4f383a0e36aecc6682fc9df058 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/43094 Reviewed-by: Tristan Corrick Tested-by: build bot (Jenkins) --- src/mainboard/lenovo/t440p/romstage.c | 37 +++++++++++++----------- src/northbridge/intel/haswell/haswell.h | 1 + src/northbridge/intel/haswell/romstage.c | 6 ++++ 3 files changed, 27 insertions(+), 17 deletions(-) diff --git a/src/mainboard/lenovo/t440p/romstage.c b/src/mainboard/lenovo/t440p/romstage.c index bd1020deb8..900bef5d87 100644 --- a/src/mainboard/lenovo/t440p/romstage.c +++ b/src/mainboard/lenovo/t440p/romstage.c @@ -23,6 +23,26 @@ void mainboard_config_rcba(void) RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); } +void mb_late_romstage_setup(void) +{ + u8 enable_peg; + if (get_option(&enable_peg, "enable_dual_graphics") != CB_SUCCESS) + enable_peg = 0; + + bool power_en = pmh7_dgpu_power_state(); + + if (enable_peg != power_en) + pmh7_dgpu_power_enable(!power_en); + + if (!enable_peg) { + // Hide disabled dGPU device + u32 reg32 = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN); + reg32 &= ~DEVEN_D1F0EN; + + pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); + } +} + void mainboard_romstage_entry(void) { struct pei_data pei_data = { @@ -77,21 +97,4 @@ void mainboard_romstage_entry(void) }; romstage_common(&romstage_params); - - u8 enable_peg; - if (get_option(&enable_peg, "enable_dual_graphics") != CB_SUCCESS) - enable_peg = 0; - - bool power_en = pmh7_dgpu_power_state(); - - if (enable_peg != power_en) - pmh7_dgpu_power_enable(!power_en); - - if (!enable_peg) { - // Hide disabled dGPU device - u32 reg32 = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN); - reg32 &= ~DEVEN_D1F0EN; - - pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); - } } diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index fa32ecad7c..7fb24c8935 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -195,6 +195,7 @@ struct romstage_params { void (*copy_spd)(struct pei_data *peid); }; void romstage_common(const struct romstage_params *params); +void mb_late_romstage_setup(void); /* optional */ void haswell_early_initialization(void); void haswell_late_initialization(void); diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c index 8cf2e7ca71..ae9d707d90 100644 --- a/src/northbridge/intel/haswell/romstage.c +++ b/src/northbridge/intel/haswell/romstage.c @@ -13,6 +13,10 @@ #include #include +void __weak mb_late_romstage_setup(void) +{ +} + void romstage_common(const struct romstage_params *params) { int wake_from_s3; @@ -77,5 +81,7 @@ void romstage_common(const struct romstage_params *params) romstage_handoff_init(wake_from_s3); + mb_late_romstage_setup(); + post_code(0x3f); }