soc/intel/cannonlake: Fix UART2 serial log broken issue

Cannonlake rvp serial log has been regressed with commit
I7eea910e065242689e87adac41281131674b39af(soc/intel/cannonlake:
Clean up UART code) because of common UART code is unable to
link all __weak function implementation from SoC uart.c due
to existing macro #define __SIMPLE_DEVICE__. Hence UART2 PCI
device resource programming is different than what it's been programmed
before.

This patch ensures UART2 PCI device resource enumeration is
working and we are getting serial log as expected.

Change-Id: I1f9df5e8d6490090ed65b06bdd0b40f824d36a8a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22862
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/cannonlake/uart.c

@@ -13,8 +13,6 @@
  * GNU General Public License for more details.
  */
 
-#define __SIMPLE_DEVICE__
-
 #include <assert.h>
 #include <cbmem.h>
 #include <console/uart.h>
@@ -30,6 +28,7 @@
 #include <soc/pci_devs.h>
 #include <soc/pcr_ids.h>
 
+#if !ENV_RAMSTAGE
 /* Serial IO UART controller legacy mode */
 #define PCR_SERIAL_IO_GPPRVRW7		0x618
 #define PCR_SIO_PCH_LEGACY_UART(idx)	(1 << (idx))
@@ -52,14 +51,6 @@ static const struct port {
 	}
 };
 
-#if IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM)
-uintptr_t uart_platform_base(int idx)
-{
-	/* We can only have one serial console at a time */
-	return UART_BASE_0_ADDR(idx);
-}
-#endif
-
 void pch_uart_init(void)
 {
 	uintptr_t base;
@@ -85,6 +76,15 @@ void pch_uart_init(void)
 
 	gpio_configure_pads(p->pads, ARRAY_SIZE(p->pads));
 }
+#endif
+
+#if IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM)
+uintptr_t uart_platform_base(int idx)
+{
+	/* We can only have one serial console at a time */
+	return UART_BASE_0_ADDR(idx);
+}
+#endif
 
 device_t pch_uart_get_debug_controller(void)
 {