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ChromeOS: Drop filling ECFW_RW/RO state in CNVS 

This field was never meant to be filled out by coreboot, because it
can't know what the right value for this will be by the time the OS
is running, so anything coreboot could fill in here is premature.

This field is only read by the chromeos-specific `crossystem` utility,
not by kernel code, so if one does not run through depthcharge there'll
be many more broken assumptions in CNVS anyway.

Change-Id: Ia56b3a3fc82f1b8247a6ee512fe960e9d3d87585
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Kyösti Mälkki 2022-03-29 00:44:51 +03:00
parent e50bb8fc9e
commit 740eee5eec
6 changed files with 0 additions and 38 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/include/bootmode.h
View File

@ -14,7 +14,6 @@ int clear_recovery_mode_switch(void);
int get_wipeout_mode_switch(void);
int get_lid_switch(void);
int get_ec_is_trusted(void);
bool mainboard_ec_running_ro(void);
/* Return 1 if display initialization is required. 0 if not. */
int display_init_required(void);

9
src/mainboard/google/butterfly/chromeos.c
View File

@ -48,15 +48,6 @@ int get_recovery_mode_switch(void)
return 0;
}
bool mainboard_ec_running_ro(void)
{
// TODO: MLR
// The firmware read/write status is a "virtual" switch and
// will be handled elsewhere. Until then hard-code to
// read/write instead of read-only for developer mode.
return false;
}
static const struct cros_gpio cros_gpios[] = {
CROS_GPIO_REC_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
CROS_GPIO_WP_AL(WP_GPIO, CROS_GPIO_DEVICE_NAME),

5
src/mainboard/google/parrot/chromeos.c
View File

@ -46,11 +46,6 @@ int get_recovery_mode_switch(void)
return !get_gpio(GPIO_REC_MODE);
}
bool mainboard_ec_running_ro(void)
{
return get_recovery_mode_switch();
}
static const struct cros_gpio cros_gpios[] = {
CROS_GPIO_REC_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
CROS_GPIO_WP_AL(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME),

5
src/mainboard/google/stout/chromeos.c
View File

@ -74,11 +74,6 @@ int get_recovery_mode_switch(void)
return ec_in_rec_mode;
}
bool mainboard_ec_running_ro(void)
{
return !!get_recovery_mode_switch();
}
static const struct cros_gpio cros_gpios[] = {
CROS_GPIO_REC_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
CROS_GPIO_WP_AL(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME),

5
src/mainboard/samsung/lumpy/chromeos.c
View File

@ -85,11 +85,6 @@ void init_bootmode_straps(void)
pci_s_write_config32(dev, SATA_SP, flags);
}
bool mainboard_ec_running_ro(void)
{
return !ec_read(0xcb);
}
static const struct cros_gpio cros_gpios[] = {
CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME),
CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME),

13
src/vendorcode/google/chromeos/gnvs.c
View File

@ -32,8 +32,6 @@ static size_t chromeos_vpd_region(const char *region, uintptr_t *base)
return region_device_sz(&vpd);
}
__weak bool mainboard_ec_running_ro(void) { return true; }
void chromeos_init_chromeos_acpi(void)
{
size_t vpd_size;
@ -58,17 +56,6 @@ void chromeos_init_chromeos_acpi(void)
chromeos_acpi->vpd_rw_base = vpd_base;
chromeos_acpi->vpd_rw_size = vpd_size;
}
/* EC can override to ECFW_RW. */
chromeos_acpi->vbt2 = ACTIVE_ECFW_RO;
if (CONFIG(EC_GOOGLE_CHROMEEC)) {
if (!google_ec_running_ro())
chromeos_acpi->vbt2 = ACTIVE_ECFW_RW;
} else {
if (!mainboard_ec_running_ro())
chromeos_acpi->vbt2 = ACTIVE_ECFW_RW;
}
}
void chromeos_set_me_hash(u32 *hash, int len)