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Final set of smp_write_bus -> mptable_write_buses changes. 

Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6114 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Patrick Georgi 2010-11-22 14:14:56 +00:00 committed by Patrick Georgi
parent 394965dd64
commit 7411eabcdb
31 changed files with 55 additions and 290 deletions
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15
src/mainboard/amd/serengeti_cheetah/get_bus_conf.c
View File

@ -109,11 +109,6 @@ void get_bus_conf(void)
dev = dev_find_slot(m->bus_8111_0, PCI_DEVFN(sysconf.sbdn,0));
if (dev) {
m->bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
#if CONFIG_HT_CHAIN_END_UNITID_BASE >= CONFIG_HT_CHAIN_UNITID_BASE
m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
m->bus_isa++;
// printk(BIOS_DEBUG, "bus_isa=%d\n",bus_isa);
#endif
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8111_0, sysconf.sbdn);
@ -132,11 +127,6 @@ void get_bus_conf(void)
dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1,0));
if (dev) {
m->bus_8132_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE
m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
m->bus_isa++;
// printk(BIOS_DEBUG, "bus_isa=%d\n",bus_isa);
#endif
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132_0, m->sbdn3+1);
@ -172,9 +162,6 @@ void get_bus_conf(void)
dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1,0));
if (dev) {
m->bus_8132a[j][2] = pci_read_config8(dev, PCI_SECONDARY_BUS);
m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
m->bus_isa++;
// printk(BIOS_DEBUG, "bus_isa=%d\n",bus_isa);
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132a[j][0], m->sbdn3a[j]+1);
@ -192,8 +179,6 @@ void get_bus_conf(void)
if (dev) {
m->bus_8151[j][1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
// printk(BIOS_DEBUG, "bus_8151_1=%d\n",bus_8151[j][1]);
m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
m->bus_isa++;
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8151[j][0], m->sbdn5[j]+1);

1
src/mainboard/amd/serengeti_cheetah/mb_sysconf.h
View File

@ -3,7 +3,6 @@
#define MB_SYSCONF_H
struct mb_sysconf_t {
unsigned char bus_isa;
unsigned char bus_8132_0;
unsigned char bus_8132_1;
unsigned char bus_8132_2;

16
src/mainboard/amd/serengeti_cheetah/mptable.c
View File

@ -13,8 +13,7 @@
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
unsigned char bus_num;
int i, j;
int i, j, bus_isa;
struct mb_sysconf_t *m;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@ -27,12 +26,7 @@ static void *smp_write_config_table(void *v)
m = sysconf.mb;
/*Bus: Bus ID Type*/
/* define bus and isa numbers */
for(bus_num = 0; bus_num < m->bus_isa; bus_num++) {
smp_write_bus(mc, bus_num, "PCI ");
}
smp_write_bus(mc, m->bus_isa, "ISA ");
mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/
smp_write_ioapic(mc, m->apicid_8111, 0x11, IO_APIC_ADDR); //8111
@ -83,7 +77,7 @@ static void *smp_write_config_table(void *v)
}
mptable_add_isa_interrupts(mc, m->bus_isa, m->apicid_8111, 0);
mptable_add_isa_interrupts(mc, bus_isa, m->apicid_8111, 0);
/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
//??? What
@ -161,8 +155,8 @@ static void *smp_write_config_table(void *v)
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0);
smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1);
smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */

18
src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c
View File

@ -108,10 +108,6 @@ void get_bus_conf(void)
m = sysconf.mb;
for(i=0;i<256; i++) {
m->bus_type[i] = 0;
}
sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
for(i=0;i<sysconf.hc_possible_num; i++) {
sysconf.pci1234[i] = pci1234x[i];
@ -120,8 +116,6 @@ void get_bus_conf(void)
get_pci1234();
m->bus_type[0] = 1; //pci
sysconf.sbdn = (sysconf.hcdn[0] >> 8) & 0xff;
m->sbdn3 = sysconf.hcdn[0] & 0xff;
@ -152,18 +146,6 @@ void get_bus_conf(void)
printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132_0, m->sbdn3+1);
}
for(i=0; i< sysconf.hc_possible_num; i++) {
if(!(sysconf.pci1234[i] & 0x1) ) continue;
u32 busn = (sysconf.pci1234[i] >> 12) & 0xff;
u32 busn_max = (sysconf.pci1234[i] >> 20) & 0xff;
for (j = busn; j <= busn_max; j++)
m->bus_type[j] = 1;
if(m->bus_isa <= busn_max)
m->bus_isa = busn_max + 1;
printk(BIOS_DEBUG, "i=%d bus range: [%x, %x] bus_isa=%x\n",i, busn, busn_max, m->bus_isa);
}
/* HT chain 1 */
j=0;
for(i=1; i< sysconf.hc_possible_num; i++) {

2
src/mainboard/amd/serengeti_cheetah_fam10/mb_sysconf.h
View File

@ -22,7 +22,6 @@
#define MB_SYSCONF_H
struct mb_sysconf_t {
u8 bus_isa;
u8 bus_8132_0;
u8 bus_8132_1;
u8 bus_8132_2;
@ -38,7 +37,6 @@ struct mb_sysconf_t {
u32 sbdn3;
u32 sbdn3a[31];
u32 sbdn5[31];
u32 bus_type[256];
};
#endif

16
src/mainboard/amd/serengeti_cheetah_fam10/mptable.c
View File

@ -31,7 +31,7 @@
static void *smp_write_config_table(void *v)
{
int i, j;
int i, j, bus_isa;
struct mp_config_table *mc;
struct mb_sysconf_t *m;
@ -45,13 +45,7 @@ static void *smp_write_config_table(void *v)
m = sysconf.mb;
/*Bus: Bus ID Type*/
/* define bus and isa numbers */
for(j= 0; j < 256 ; j++) {
if(m->bus_type[j])
smp_write_bus(mc, j, "PCI ");
}
smp_write_bus(mc, m->bus_isa, "ISA ");
mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/
smp_write_ioapic(mc, m->apicid_8111, 0x11, IO_APIC_ADDR); //8111
@ -102,7 +96,7 @@ static void *smp_write_config_table(void *v)
}
mptable_add_isa_interrupts(mc, m->bus_isa, m->apicid_8111, 0);
mptable_add_isa_interrupts(mc, bus_isa, m->apicid_8111, 0);
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
//??? What
@ -185,8 +179,8 @@ static void *smp_write_config_table(void *v)
/* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0);
smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1);
smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */

18
src/mainboard/asus/a8n_e/get_bus_conf.c
View File

@ -38,7 +38,6 @@
* mptable and acpi_tables.
*/
/* busnum is default */
unsigned char bus_isa;
unsigned char bus_ck804[6];
unsigned apicid_ck804;
@ -59,17 +58,13 @@ unsigned hcdnx[] = {
0x20202020, /* A8N-E has only one ht-chain */
};
unsigned bus_type[256];
static unsigned get_bus_conf_done = 0;
void get_bus_conf(void)
{
unsigned apicid_base, sbdn;
device_t dev;
int i, j;
int i;
if (get_bus_conf_done == 1)
return; /* Do it only once. */
@ -91,15 +86,9 @@ void get_bus_conf(void)
for (i = 0; i < 6; i++)
bus_ck804[i] = 0;
for (i = 0; i < 256; i++)
bus_type[i] = 0;
bus_type[0] = 1; /* PCI */
bus_ck804[0] = (sysconf.pci1234[0] >> 16) & 0xff;
bus_type[bus_ck804[0]] = 1;
/* CK804 */
dev = dev_find_slot(bus_ck804[0], PCI_DEVFN(sbdn + 0x09, 0));
if (dev) {
@ -119,14 +108,9 @@ void get_bus_conf(void)
PCI_DEVFN(sbdn + 0x0b + i - 2, 0));
if (dev) {
bus_ck804[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_isa++;
for (j = bus_ck804[i]; j < bus_isa; j++)
bus_type[j] = 1;
} else {
printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n",
bus_ck804[0], sbdn + 0x0b + i - 2);
bus_isa = bus_ck804[i - 1] + 1;
}
}

12
src/mainboard/asus/a8n_e/mptable.c
View File

@ -28,16 +28,14 @@
#include <stdint.h>
#include <cpu/amd/amdk8_sysconf.h>
extern unsigned char bus_isa;
extern unsigned char bus_ck804[6];
extern unsigned apicid_ck804;
extern unsigned bus_type[256];
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
unsigned sbdn;
int bus_num;
int bus_isa;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@ -48,13 +46,7 @@ static void *smp_write_config_table(void *v)
get_bus_conf();
sbdn = sysconf.sbdn;
/* Bus: Bus ID Type */
/* Define numbers for PCI and ISA bus. */
for (bus_num = 0; bus_num < 256; bus_num++) {
if (bus_type[bus_num])
smp_write_bus(mc, bus_num, "PCI ");
}
smp_write_bus(mc, bus_isa, "ISA ");
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
{

12
src/mainboard/asus/a8v-e_deluxe/mptable.c
View File

@ -27,7 +27,7 @@
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa = 42;
int bus_isa;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@ -35,15 +35,7 @@ static void *smp_write_config_table(void *v)
smp_write_processors(mc);
/* Bus: Bus ID Type */
smp_write_bus(mc, 0, "PCI ");
smp_write_bus(mc, 1, "PCI ");
smp_write_bus(mc, 2, "PCI ");
smp_write_bus(mc, 3, "PCI ");
smp_write_bus(mc, 4, "PCI ");
smp_write_bus(mc, 5, "PCI ");
smp_write_bus(mc, 6, "PCI ");
smp_write_bus(mc, bus_isa, "ISA ");
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, IO_APIC_ADDR);

12
src/mainboard/asus/a8v-e_se/mptable.c
View File

@ -27,7 +27,7 @@
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa = 42;
int bus_isa;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@ -35,15 +35,7 @@ static void *smp_write_config_table(void *v)
smp_write_processors(mc);
/* Bus: Bus ID Type */
smp_write_bus(mc, 0, "PCI ");
smp_write_bus(mc, 1, "PCI ");
smp_write_bus(mc, 2, "PCI ");
smp_write_bus(mc, 3, "PCI ");
smp_write_bus(mc, 4, "PCI ");
smp_write_bus(mc, 5, "PCI ");
smp_write_bus(mc, 6, "PCI ");
smp_write_bus(mc, bus_isa, "ISA ");
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, IO_APIC_ADDR);

13
src/mainboard/intel/eagleheights/mptable.c
View File

@ -61,9 +61,9 @@
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
unsigned char bus_num, bus_chipset, bus_isa, bus_pci;
unsigned char bus_chipset, bus_pci;
unsigned char bus_pcie_a, bus_pcie_a1, bus_pcie_b;
int i;
int bus_isa, i;
uint32_t pin, route;
device_t dev;
struct resource *res;
@ -89,12 +89,9 @@ static void *smp_write_config_table(void *v)
dev = dev_find_slot(0, PCI_DEVFN(0x1E,0));
if (dev) {
bus_pci = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_isa++;
} else {
printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1e.0, using defaults\n");
bus_pci = 6;
bus_isa = 7;
}
dev = dev_find_slot(0, PCI_DEVFN(2,0));
@ -121,11 +118,7 @@ static void *smp_write_config_table(void *v)
bus_pcie_b = 3;
}
/*Bus: Bus ID Type*/
for(bus_num = 0; bus_num < bus_isa; bus_num++) {
smp_write_bus(mc, bus_num, "PCI ");
}
smp_write_bus(mc, bus_isa, "ISA ");
mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/
smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);

12
src/mainboard/intel/jarrell/mptable.c
View File

@ -8,8 +8,7 @@
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
unsigned char bus_num;
unsigned char bus_isa;
int bus_isa;
unsigned char bus_pxhd_1;
unsigned char bus_pxhd_2;
unsigned char bus_pxhd_3 = 0;
@ -31,14 +30,11 @@ static void *smp_write_config_table(void *v)
dev = dev_find_slot(0, PCI_DEVFN(0x1e,0));
if (dev) {
bus_ich5r_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_isa++;
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1f.0, using defaults\n");
bus_ich5r_1 = 4;
bus_isa = 5;
}
/* pxhd-1 */
dev = dev_find_slot(1, PCI_DEVFN(0x0,0));
@ -88,11 +84,7 @@ static void *smp_write_config_table(void *v)
}
}
/* define bus and isa numbers */
for(bus_num = 0; bus_num < bus_isa; bus_num++) {
smp_write_bus(mc, bus_num, "PCI ");
}
smp_write_bus(mc, bus_isa, "ISA ");
mptable_write_buses(mc, NULL, &bus_isa);
/* IOAPIC handling */

8
src/mainboard/intel/mtarvon/mptable.c
View File

@ -29,7 +29,7 @@
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
u8 bus_isa = 7;
int bus_isa;
u8 bus_pci = 6;
u8 bus_pcie_a = 1;
@ -39,11 +39,7 @@ static void *smp_write_config_table(void *v)
smp_write_processors(mc);
/* Define bus numbers */
smp_write_bus(mc, 0, "PCI ");
smp_write_bus(mc, bus_pci, "PCI ");
smp_write_bus(mc, bus_pcie_a, "PCI ");
smp_write_bus(mc, bus_isa, "ISA ");
mptable_write_buses(mc, NULL, &bus_isa);
/* IOAPIC handling */
smp_write_ioapic(mc, 0x01, 0x20, IO_APIC_ADDR);

12
src/mainboard/intel/truxton/mptable.c
View File

@ -27,8 +27,7 @@
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
u8 bus_num;
u8 bus_isa;
int bus_isa;
u8 bus_pea0 = 0;
u8 bus_pea1 = 0;
u8 bus_aioc;
@ -44,13 +43,10 @@ static void *smp_write_config_table(void *v)
dev = dev_find_slot(0, PCI_DEVFN(0x04,0));
if (dev) {
bus_aioc = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_isa++;
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI 0:04.0\n");
bus_aioc = 0;
bus_isa = 9;
}
/* PCIe A0 */
dev = dev_find_slot(0, PCI_DEVFN(0x02,0));
@ -71,11 +67,7 @@ static void *smp_write_config_table(void *v)
bus_pea1 = 0;
}
/* define bus and isa numbers */
for(bus_num = 0; bus_num < bus_isa; bus_num++) {
smp_write_bus(mc, bus_num, "PCI ");
}
smp_write_bus(mc, bus_isa, "ISA ");
mptable_write_buses(mc, NULL, &bus_isa);
/* IOAPIC handling */
smp_write_ioapic(mc, 0x8, 0x20, IO_APIC_ADDR);

1
src/mainboard/intel/xe7501devkit/bus.h
View File

@ -12,6 +12,5 @@
#define PCI_BUS_P64H2_1_B 5 // P64H2#1 bus B
#define PCI_BUS_P64H2_1_A 6 // P64H2#1 bus A
#define PCI_BUS_ICH3 7 // ICH3-S
#define SUPERIO_BUS 8 // (arbitrary but unique bus #)
#endif // XE7501DEVKIT_BUS_H_INCLUDED

18
src/mainboard/intel/xe7501devkit/mptable.c
View File

@ -15,19 +15,7 @@
#define INT_D 3
#define PCI_IRQ(dev, intLine) (((dev)<<2) | intLine)
static void xe7501devkit_register_buses(struct mp_config_table *mc)
{
// Bus ID, Bus Type
smp_write_bus(mc, PCI_BUS_CHIPSET, BUSTYPE_PCI);
smp_write_bus(mc, PCI_BUS_E7501_HI_B, BUSTYPE_PCI);
smp_write_bus(mc, PCI_BUS_P64H2_2_B, BUSTYPE_PCI);
smp_write_bus(mc, PCI_BUS_P64H2_2_A, BUSTYPE_PCI);
smp_write_bus(mc, PCI_BUS_E7501_HI_D, BUSTYPE_PCI);
smp_write_bus(mc, PCI_BUS_P64H2_1_B, BUSTYPE_PCI);
smp_write_bus(mc, PCI_BUS_P64H2_1_A, BUSTYPE_PCI);
smp_write_bus(mc, PCI_BUS_ICH3, BUSTYPE_PCI);
smp_write_bus(mc, SUPERIO_BUS, BUSTYPE_ISA);
}
static int bus_isa;
static void xe7501devkit_register_ioapics(struct mp_config_table *mc)
{
@ -126,7 +114,7 @@ static void xe7501devkit_register_interrupts(struct mp_config_table *mc)
// TODO: Not sure how to handle BT_INTR# signals from the P64H2s. Do we even need to, in APIC mode?
mptable_add_isa_interrupts(mc, SUPERIO_BUS, IOAPIC_ICH3, 0);
mptable_add_isa_interrupts(mc, bus_isa, IOAPIC_ICH3, 0);
}
static void *smp_write_config_table(void* v)
@ -139,7 +127,7 @@ static void *smp_write_config_table(void* v)
smp_write_processors(mc);
xe7501devkit_register_buses(mc);
mptable_write_buses(mc, NULL, &bus_isa);
xe7501devkit_register_ioapics(mc);
xe7501devkit_register_interrupts(mc);

4
src/mainboard/supermicro/h8dme/get_bus_conf.c
View File

@ -34,7 +34,6 @@
// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
//busnum is default
unsigned char bus_isa;
unsigned char bus_mcp55[8]; //1
unsigned apicid_mcp55;
@ -124,12 +123,9 @@ void get_bus_conf(void)
dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn + 0x0a + i - 2 , 0));
if (dev) {
bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_isa++;
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_mcp55[0], sbdn + 0x0a + i - 2 );
bus_isa = bus_mcp55[i-1]+1;
}
}

11
src/mainboard/supermicro/h8dme/mptable.c
View File

@ -26,7 +26,6 @@
#include <stdint.h>
#include <cpu/amd/amdk8_sysconf.h>
extern unsigned char bus_isa;
extern unsigned char bus_mcp55[8]; //1
extern unsigned apicid_mcp55;
@ -37,8 +36,7 @@ static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
unsigned sbdn;
unsigned char bus_num;
int i,j;
int i, j, bus_isa;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@ -49,12 +47,7 @@ static void *smp_write_config_table(void *v)
get_bus_conf();
sbdn = sysconf.sbdn;
/*Bus: Bus ID Type*/
/* define bus and isa numbers */
for(bus_num = 0; bus_num < bus_isa; bus_num++) {
smp_write_bus(mc, bus_num, "PCI ");
}
smp_write_bus(mc, bus_isa, "ISA ");
mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/
{

4
src/mainboard/supermicro/h8dmr/get_bus_conf.c
View File

@ -34,7 +34,6 @@
// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
//busnum is default
unsigned char bus_isa;
unsigned char bus_mcp55[8]; //1
unsigned apicid_mcp55;
@ -124,12 +123,9 @@ void get_bus_conf(void)
dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn + 0x0a + i - 2 , 0));
if (dev) {
bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_isa++;
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_mcp55[0], sbdn + 0x0a + i - 2 );
bus_isa = bus_mcp55[i-1]+1;
}
}

11
src/mainboard/supermicro/h8dmr/mptable.c
View File

@ -26,7 +26,6 @@
#include <stdint.h>
#include <cpu/amd/amdk8_sysconf.h>
extern unsigned char bus_isa;
extern unsigned char bus_mcp55[8]; //1
extern unsigned apicid_mcp55;
@ -37,8 +36,7 @@ static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
unsigned sbdn;
unsigned char bus_num;
int i,j;
int i, j, bus_isa;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@ -49,12 +47,7 @@ static void *smp_write_config_table(void *v)
get_bus_conf();
sbdn = sysconf.sbdn;
/*Bus: Bus ID Type*/
/* define bus and isa numbers */
for(bus_num = 0; bus_num < bus_isa; bus_num++) {
smp_write_bus(mc, bus_num, "PCI ");
}
smp_write_bus(mc, bus_isa, "ISA ");
mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/
{

15
src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c
View File

@ -73,7 +73,7 @@ void get_bus_conf(void)
struct mb_sysconf_t *m;
device_t dev;
int i, j;
int i;
if(get_bus_conf_done==1) return; //do it only once
@ -92,7 +92,6 @@ void get_bus_conf(void)
get_pci1234();
m->bus_type[0] = 1; //pci
sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain
m->bus_mcp55[0] = (sysconf.pci1234[0] >> 12) & 0xff;
@ -115,18 +114,6 @@ void get_bus_conf(void)
}
}
for(i=0; i< sysconf.hc_possible_num; i++) {
if(!(sysconf.pci1234[i] & 0x1) ) continue;
unsigned busn = (sysconf.pci1234[i] >> 12) & 0xff;
unsigned busn_max = (sysconf.pci1234[i] >> 20) & 0xff;
for (j = busn; j <= busn_max; j++)
m->bus_type[j] = 1;
if(m->bus_isa <= busn_max)
m->bus_isa = busn_max + 1;
printk(BIOS_DEBUG, "i=%d bus range: [%x, %x] bus_isa=%x\n",i, busn, busn_max, m->bus_isa);
}
/*I/O APICs: APIC ID Version State Address*/
#if CONFIG_LOGICAL_CPUS==1
apicid_base = get_apicid_base(1);

3
src/mainboard/supermicro/h8dmr_fam10/mb_sysconf.h
View File

@ -23,11 +23,8 @@
#define MB_SYSCONF_H
struct mb_sysconf_t {
unsigned char bus_isa;
unsigned char bus_mcp55[8]; //1
unsigned apicid_mcp55;
unsigned bus_type[256];
};
#endif

16
src/mainboard/supermicro/h8dmr_fam10/mptable.c
View File

@ -32,7 +32,7 @@ static void *smp_write_config_table(void *v)
struct mp_config_table *mc;
struct mb_sysconf_t *m;
unsigned sbdn;
int i,j;
int i, j, bus_isa;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@ -44,13 +44,7 @@ static void *smp_write_config_table(void *v)
sbdn = sysconf.sbdn;
m = sysconf.mb;
/*Bus: Bus ID Type*/
/* define bus and isa numbers */
for(j= 0; j < 256 ; j++) {
if(m->bus_type[j])
smp_write_bus(mc, j, "PCI ");
}
smp_write_bus(mc, m->bus_isa, "ISA ");
mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/
{
@ -79,7 +73,7 @@ static void *smp_write_config_table(void *v)
}
mptable_add_isa_interrupts(mc, m->bus_isa, m->apicid_mcp55, 0);
mptable_add_isa_interrupts(mc, bus_isa, m->apicid_mcp55, 0);
/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+1)<<2)|1, m->apicid_mcp55, 0xa);
@ -110,8 +104,8 @@ static void *smp_write_config_table(void *v)
}
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0);
smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1);
smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */

17
src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c
View File

@ -75,7 +75,7 @@ void get_bus_conf(void)
struct mb_sysconf_t *m;
device_t dev;
int i, j;
int i;
if(get_bus_conf_done==1) return; //do it only once
@ -94,7 +94,6 @@ void get_bus_conf(void)
get_pci1234();
m->bus_type[0] = 1; //pci
sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain
m->bus_mcp55[0] = (sysconf.pci1234[0] >> 12) & 0xff;
@ -131,20 +130,6 @@ void get_bus_conf(void)
/* 8132_2 */
dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(sbdn3 + 1, 0));
m->bus_8132_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
m->bus_isa++;
for(i=0; i< sysconf.hc_possible_num; i++) {
if(!(sysconf.pci1234[i] & 0x1) ) continue;
unsigned busn = (sysconf.pci1234[i] >> 12) & 0xff;
unsigned busn_max = (sysconf.pci1234[i] >> 20) & 0xff;
for (j = busn; j <= busn_max; j++)
m->bus_type[j] = 1;
if(m->bus_isa <= busn_max)
m->bus_isa = busn_max + 1;
printk(BIOS_DEBUG, "i=%d bus range: [%x, %x] bus_isa=%x\n",i, busn, busn_max, m->bus_isa);
}
/*I/O APICs: APIC ID Version State Address*/
#if CONFIG_LOGICAL_CPUS==1

2
src/mainboard/supermicro/h8qme_fam10/mb_sysconf.h
View File

@ -23,10 +23,8 @@
#define MB_SYSCONF_H
struct mb_sysconf_t {
unsigned char bus_isa;
unsigned char bus_mcp55[8]; //1
unsigned apicid_mcp55;
unsigned bus_type[256];
unsigned char bus_8132_0; //7
unsigned char bus_8132_1; //8

16
src/mainboard/supermicro/h8qme_fam10/mptable.c
View File

@ -34,7 +34,7 @@ static void *smp_write_config_table(void *v)
struct mp_config_table *mc;
struct mb_sysconf_t *m;
unsigned sbdn;
int i,j;
int i, j, bus_isa;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@ -46,13 +46,7 @@ static void *smp_write_config_table(void *v)
sbdn = sysconf.sbdn;
m = sysconf.mb;
/*Bus: Bus ID Type*/
/* define bus and isa numbers */
for(j= 0; j < 256 ; j++) {
if(m->bus_type[j])
smp_write_bus(mc, j, "PCI ");
}
smp_write_bus(mc, m->bus_isa, "ISA ");
mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/
{
@ -81,7 +75,7 @@ static void *smp_write_config_table(void *v)
}
mptable_add_isa_interrupts(mc, m->bus_isa, m->apicid_mcp55, 0);
mptable_add_isa_interrupts(mc, bus_isa, m->apicid_mcp55, 0);
/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+1)<<2)|1, m->apicid_mcp55, 0x5); /* 5 SMBus, OK */
@ -108,8 +102,8 @@ static void *smp_write_config_table(void *v)
}
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0);
smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1);
smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */

12
src/mainboard/supermicro/x6dai_g/mptable.c
View File

@ -8,8 +8,7 @@
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
unsigned char bus_num;
unsigned char bus_isa;
int bus_isa;
unsigned char bus_6300;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@ -25,21 +24,14 @@ static void *smp_write_config_table(void *v)
dev = dev_find_slot(0, PCI_DEVFN(0x1e,0));
if (dev) {
bus_6300 = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_isa++;
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1e.0, using defaults\n");
bus_6300 = 5;
bus_isa = 6;
}
}
/* define bus and isa numbers */
for(bus_num = 0; bus_num < bus_isa; bus_num++) {
smp_write_bus(mc, bus_num, "PCI ");
}
smp_write_bus(mc, bus_isa, "ISA ");
mptable_write_buses(mc, NULL, &bus_isa);
/* IOAPIC handling */

12
src/mainboard/supermicro/x6dhe_g/mptable.c
View File

@ -8,8 +8,7 @@
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
unsigned char bus_num;
unsigned char bus_isa;
int bus_isa;
unsigned char bus_pxhd_1;
unsigned char bus_pxhd_2;
unsigned char bus_esb6300_1;
@ -36,12 +35,9 @@ static void *smp_write_config_table(void *v)
dev = dev_find_slot(0, PCI_DEVFN(0x1e,0));
if (dev) {
bus_esb6300_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_isa++;
} else {
printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1e.0, using defaults\n");
bus_esb6300_2 = 7;
bus_isa = 8;
}
/* pxhd-1 */
dev = dev_find_slot(1, PCI_DEVFN(0x0,0));
@ -61,11 +57,7 @@ static void *smp_write_config_table(void *v)
}
}
/* define bus and isa numbers */
for(bus_num = 0; bus_num < bus_isa; bus_num++) {
smp_write_bus(mc, bus_num, "PCI ");
}
smp_write_bus(mc, bus_isa, "ISA ");
mptable_write_buses(mc, NULL, &bus_isa);
/* IOAPIC handling */

12
src/mainboard/supermicro/x6dhe_g2/mptable.c
View File

@ -8,8 +8,7 @@
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
unsigned char bus_num;
unsigned char bus_isa;
int bus_isa;
unsigned char bus_pxhd_1;
unsigned char bus_pxhd_2;
unsigned char bus_esb6300_1;
@ -36,12 +35,9 @@ static void *smp_write_config_table(void *v)
dev = dev_find_slot(0, PCI_DEVFN(0x1e,0));
if (dev) {
bus_esb6300_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_isa++;
} else {
printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1e.0, using defaults\n");
bus_esb6300_2 = 7;
bus_isa = 8;
}
/* pxhd-1 */
dev = dev_find_slot(1, PCI_DEVFN(0x0,0));
@ -61,11 +57,7 @@ static void *smp_write_config_table(void *v)
}
}
/* define bus and isa numbers */
for(bus_num = 0; bus_num < bus_isa; bus_num++) {
smp_write_bus(mc, bus_num, "PCI ");
}
smp_write_bus(mc, bus_isa, "ISA ");
mptable_write_buses(mc, NULL, &bus_isa);
/* IOAPIC handling */

12
src/mainboard/supermicro/x6dhr_ig/mptable.c
View File

@ -8,8 +8,7 @@
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
unsigned char bus_num;
unsigned char bus_isa;
int bus_isa;
unsigned char bus_pxhd_1;
unsigned char bus_pxhd_2;
unsigned char bus_pxhd_3;
@ -29,14 +28,11 @@ static void *smp_write_config_table(void *v)
dev = dev_find_slot(0, PCI_DEVFN(0x1e,0));
if (dev) {
bus_ich5r_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_isa++;
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1f.0, using defaults\n");
bus_ich5r_1 = 9;
bus_isa = 10;
}
/* pxhd-1 */
dev = dev_find_slot(2, PCI_DEVFN(0x0,0));
@ -86,11 +82,7 @@ static void *smp_write_config_table(void *v)
}
/* define bus and isa numbers */
for(bus_num = 0; bus_num < bus_isa; bus_num++) {
smp_write_bus(mc, bus_num, "PCI ");
}
smp_write_bus(mc, bus_isa, "ISA ");
mptable_write_buses(mc, NULL, &bus_isa);
/* IOAPIC handling */

12
src/mainboard/supermicro/x6dhr_ig2/mptable.c
View File

@ -8,8 +8,7 @@
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
unsigned char bus_num;
unsigned char bus_isa;
int bus_isa;
unsigned char bus_pxhd_1;
unsigned char bus_pxhd_2;
unsigned char bus_pxhd_3;
@ -29,14 +28,11 @@ static void *smp_write_config_table(void *v)
dev = dev_find_slot(0, PCI_DEVFN(0x1e,0));
if (dev) {
bus_ich5r_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_isa++;
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1e.0, using defaults\n");
bus_ich5r_1 = 7;
bus_isa = 8;
}
/* pxhd-1 */
dev = dev_find_slot(1, PCI_DEVFN(0x0,0));
@ -86,11 +82,7 @@ static void *smp_write_config_table(void *v)
}
/* define bus and isa numbers */
for(bus_num = 0; bus_num < bus_isa; bus_num++) {
smp_write_bus(mc, bus_num, "PCI ");
}
smp_write_bus(mc, bus_isa, "ISA ");
mptable_write_buses(mc, NULL, &bus_isa);
/* IOAPIC handling */