soc/amd/picasso/acpi: Delete unused and invalid OperationRegions

0xc50, 0xc52, 0xc6f don't exist on Picasso. The PCI config space
registers define SATA and OHCI which are at the wrong bus locations.
I just remove the whole section since it's not used. We never access the
PCIe Error region, or the PM2 region either.

BUG=b:153001807, b:154756391
TEST=Build Trembyle

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I98aee09770f1df9f553c94580c1ee00c06a9cec1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>

src/soc/amd/picasso/acpi/pci_int.asl

@@ -1,108 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-	/* PCIe Configuration Space for CONFIG_MMCONF_BUS_NUMBER busses */
-	OperationRegion(PCFG, SystemMemory, PCBA, PCLN) /* Each bus consumes 1MB */
-		Field(PCFG, ByteAcc, NoLock, Preserve) {
-		/* Byte offsets are computed using the following technique:
-		 * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
-		 * The 8 comes from 8 functions per device, and 4096 bytes per function config space
-		*/
-		Offset(0x00088024),	/* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */
-		STB5, 32,
-		Offset(0x00098042),	/* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
-		PT0D, 1,
-		PT1D, 1,
-		PT2D, 1,
-		PT3D, 1,
-		PT4D, 1,
-		PT5D, 1,
-		PT6D, 1,
-		PT7D, 1,
-		PT8D, 1,
-		PT9D, 1,
-		Offset(0x000a0004),	/* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */
-		SBIE, 1,
-		SBME, 1,
-		Offset(0x000a0008),	/* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */
-		SBRI, 8,
-		Offset(0x000a0014),	/* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */
-		SBB1, 32,
-		Offset(0x000a0078),	/* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */
-		,14,
-		P92E, 1,		/* Port92 decode enable */
-	}
-
-	OperationRegion(SB5, SystemMemory, STB5, 0x1000)
-		Field(SB5, AnyAcc, NoLock, Preserve){
-		/* Port 0 */
-		Offset(0x120),		/* Port 0 Task file status */
-		P0ER, 1,
-		, 2,
-		P0DQ, 1,
-		, 3,
-		P0BY, 1,
-		Offset(0x128),		/* Port 0 Serial ATA status */
-		P0DD, 4,
-		, 4,
-		P0IS, 4,
-		Offset(0x12c),		/* Port 0 Serial ATA control */
-		P0DI, 4,
-		Offset(0x130),		/* Port 0 Serial ATA error */
-		, 16,
-		P0PR, 1,
-
-		/* Port 1 */
-		offset(0x1a0),		/* Port 1 Task file status */
-		P1ER, 1,
-		, 2,
-		P1DQ, 1,
-		, 3,
-		P1BY, 1,
-		Offset(0x1a8),		/* Port 1 Serial ATA status */
-		P1DD, 4,
-		, 4,
-		P1IS, 4,
-		Offset(0x1ac),		/* Port 1 Serial ATA control */
-		P1DI, 4,
-		Offset(0x1b0),		/* Port 1 Serial ATA error */
-		, 16,
-		P1PR, 1,
-
-		/* Port 2 */
-		Offset(0x220),		/* Port 2 Task file status */
-		P2ER, 1,
-		, 2,
-		P2DQ, 1,
-		, 3,
-		P2BY, 1,
-		Offset(0x228),		/* Port 2 Serial ATA status */
-		P2DD, 4,
-		, 4,
-		P2IS, 4,
-		Offset(0x22c),		/* Port 2 Serial ATA control */
-		P2DI, 4,
-		Offset(0x230),		/* Port 2 Serial ATA error */
-		, 16,
-		P2PR, 1,
-
-		/* Port 3 */
-		Offset(0x2a0),		/* Port 3 Task file status */
-		P3ER, 1,
-		, 2,
-		P3DQ, 1,
-		, 3,
-		P3BY, 1,
-		Offset(0x2a8),		/* Port 3 Serial ATA status */
-		P3DD, 4,
-		, 4,
-		P3IS, 4,
-		Offset(0x2aC),		/* Port 3 Serial ATA control */
-		P3DI, 4,
-		Offset(0x2b0),		/* Port 3 Serial ATA error */
-		, 16,
-		P3PR, 1,
-	}
-
 	Method(\_PIC, 0x01, NotSerialized)
 	{
 		If (Arg0)

src/soc/amd/picasso/acpi/pcie.asl

@@ -64,54 +64,6 @@
 		IUA3, 0x00000008,	/* Index 0xF9: UART3 */
 	}
 
-	/* PCI Error control register */
-	OperationRegion(PERC, SystemIO, 0x00000c14, 0x00000001)
-		Field(PERC, ByteAcc, NoLock, Preserve) {
-		SENS, 0x00000001,
-		PENS, 0x00000001,
-		SENE, 0x00000001,
-		PENE, 0x00000001,
-	}
-
-	/* Client Management index/data registers */
-	OperationRegion(CMT, SystemIO, 0x00000c50, 0x00000002)
-		Field(CMT, ByteAcc, NoLock, Preserve) {
-		CMTI,	8,
-		/* Client Management Data register */
-		G64E,	1,
-		G64O,	1,
-		G32O,	2,
-		,		2,
-		GPSL,	2,
-	}
-
-	/* GPM Port register */
-	OperationRegion(GPT, SystemIO, 0x00000c52, 0x00000001)
-		Field(GPT, ByteAcc, NoLock, Preserve) {
-		GPB0,1,
-		GPB1,1,
-		GPB2,1,
-		GPB3,1,
-		GPB4,1,
-		GPB5,1,
-		GPB6,1,
-		GPB7,1,
-	}
-
-	/* Flash ROM program enable register */
-	OperationRegion(FRE, SystemIO, 0x00000c6F, 0x00000001)
-		Field(FRE, ByteAcc, NoLock, Preserve) {
-		,     0x00000006,
-		FLRE, 0x00000001,
-	}
-
-	/* PM2 index/data registers */
-	OperationRegion(PM2R, SystemIO, 0x00000Cd0, 0x00000002)
-		Field(PM2R, ByteAcc, NoLock, Preserve) {
-		PM2I, 0x00000008,
-		PM2D, 0x00000008,
-	}
-
 	/* Power Management I/O registers, TODO:PMIO is quite different in SB800. */
 	OperationRegion(PIOR, SystemIO, 0x00000Cd6, 0x00000002)
 		Field(PIOR, ByteAcc, NoLock, Preserve) {