soc/amd/picasso/acpi: Delete unused and invalid OperationRegions
0xc50, 0xc52, 0xc6f don't exist on Picasso. The PCI config space registers define SATA and OHCI which are at the wrong bus locations. I just remove the whole section since it's not used. We never access the PCIe Error region, or the PM2 region either. BUG=b:153001807, b:154756391 TEST=Build Trembyle Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I98aee09770f1df9f553c94580c1ee00c06a9cec1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Raul E Rangel
Patrick Georgi
parent
1aa5cff709
commit
742abd3daf
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@ -1,108 +1,5 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* PCIe Configuration Space for CONFIG_MMCONF_BUS_NUMBER busses */
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OperationRegion(PCFG, SystemMemory, PCBA, PCLN) /* Each bus consumes 1MB */
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Field(PCFG, ByteAcc, NoLock, Preserve) {
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/* Byte offsets are computed using the following technique:
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* ((bus number + 1) * ((device number * 8) * 4096)) + register offset
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* The 8 comes from 8 functions per device, and 4096 bytes per function config space
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*/
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Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */
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STB5, 32,
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Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
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PT0D, 1,
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PT1D, 1,
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PT2D, 1,
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PT3D, 1,
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PT4D, 1,
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PT5D, 1,
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PT6D, 1,
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PT7D, 1,
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PT8D, 1,
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PT9D, 1,
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Offset(0x000a0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */
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SBIE, 1,
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SBME, 1,
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Offset(0x000a0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */
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SBRI, 8,
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Offset(0x000a0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */
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SBB1, 32,
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Offset(0x000a0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */
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,14,
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P92E, 1, /* Port92 decode enable */
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}
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OperationRegion(SB5, SystemMemory, STB5, 0x1000)
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Field(SB5, AnyAcc, NoLock, Preserve){
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/* Port 0 */
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Offset(0x120), /* Port 0 Task file status */
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P0ER, 1,
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, 2,
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P0DQ, 1,
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, 3,
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P0BY, 1,
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Offset(0x128), /* Port 0 Serial ATA status */
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P0DD, 4,
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, 4,
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P0IS, 4,
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Offset(0x12c), /* Port 0 Serial ATA control */
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P0DI, 4,
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Offset(0x130), /* Port 0 Serial ATA error */
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, 16,
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P0PR, 1,
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/* Port 1 */
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offset(0x1a0), /* Port 1 Task file status */
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P1ER, 1,
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, 2,
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P1DQ, 1,
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, 3,
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P1BY, 1,
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Offset(0x1a8), /* Port 1 Serial ATA status */
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P1DD, 4,
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, 4,
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P1IS, 4,
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Offset(0x1ac), /* Port 1 Serial ATA control */
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P1DI, 4,
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Offset(0x1b0), /* Port 1 Serial ATA error */
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, 16,
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P1PR, 1,
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/* Port 2 */
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Offset(0x220), /* Port 2 Task file status */
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P2ER, 1,
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, 2,
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P2DQ, 1,
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, 3,
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P2BY, 1,
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Offset(0x228), /* Port 2 Serial ATA status */
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P2DD, 4,
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, 4,
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P2IS, 4,
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Offset(0x22c), /* Port 2 Serial ATA control */
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P2DI, 4,
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Offset(0x230), /* Port 2 Serial ATA error */
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, 16,
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P2PR, 1,
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/* Port 3 */
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Offset(0x2a0), /* Port 3 Task file status */
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P3ER, 1,
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, 2,
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P3DQ, 1,
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, 3,
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P3BY, 1,
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Offset(0x2a8), /* Port 3 Serial ATA status */
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P3DD, 4,
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, 4,
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P3IS, 4,
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Offset(0x2aC), /* Port 3 Serial ATA control */
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P3DI, 4,
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Offset(0x2b0), /* Port 3 Serial ATA error */
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, 16,
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P3PR, 1,
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}
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Method(\_PIC, 0x01, NotSerialized)
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{
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If (Arg0)
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@ -64,54 +64,6 @@
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IUA3, 0x00000008, /* Index 0xF9: UART3 */
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}
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/* PCI Error control register */
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OperationRegion(PERC, SystemIO, 0x00000c14, 0x00000001)
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Field(PERC, ByteAcc, NoLock, Preserve) {
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SENS, 0x00000001,
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PENS, 0x00000001,
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SENE, 0x00000001,
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PENE, 0x00000001,
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}
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/* Client Management index/data registers */
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OperationRegion(CMT, SystemIO, 0x00000c50, 0x00000002)
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Field(CMT, ByteAcc, NoLock, Preserve) {
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CMTI, 8,
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/* Client Management Data register */
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G64E, 1,
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G64O, 1,
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G32O, 2,
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, 2,
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GPSL, 2,
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}
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/* GPM Port register */
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OperationRegion(GPT, SystemIO, 0x00000c52, 0x00000001)
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Field(GPT, ByteAcc, NoLock, Preserve) {
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GPB0,1,
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GPB1,1,
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GPB2,1,
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GPB3,1,
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GPB4,1,
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GPB5,1,
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GPB6,1,
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GPB7,1,
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}
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/* Flash ROM program enable register */
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OperationRegion(FRE, SystemIO, 0x00000c6F, 0x00000001)
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Field(FRE, ByteAcc, NoLock, Preserve) {
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, 0x00000006,
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FLRE, 0x00000001,
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}
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/* PM2 index/data registers */
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OperationRegion(PM2R, SystemIO, 0x00000Cd0, 0x00000002)
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Field(PM2R, ByteAcc, NoLock, Preserve) {
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PM2I, 0x00000008,
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PM2D, 0x00000008,
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}
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/* Power Management I/O registers, TODO:PMIO is quite different in SB800. */
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OperationRegion(PIOR, SystemIO, 0x00000Cd6, 0x00000002)
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Field(PIOR, ByteAcc, NoLock, Preserve) {
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