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mb/google/hatch: Kohaku: Enable DMIC1 in device tree 

The default is DMIC0 on, but Kohaku is also using DMIC1

BUG=b:133282247
BRANCH=None
TEST=arecord -D hw:0,1 -r 48000 -c 4 -f s32 4dmic.wav
make sure 4 channels recording work

Signed-off-by: Mac Chiang <mac.chiang@intel.com>
Change-Id: I2dd573e1634516bcf9876bedb92b7d9148bb0e6a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34692
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Mac Chiang 2019-08-02 11:09:24 +08:00 committed by Shelley Chen
parent 670856620d
commit 7439a7adaf
2 changed files with 5 additions and 1 deletions
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3
src/mainboard/google/hatch/variants/baseboard/devicetree.cb
View File

@ -168,11 +168,12 @@ chip soc/intel/cannonlake
register "PcieClkSrcUsage[3]" = "13" register "PcieClkSrcUsage[3]" = "13"
register "PcieClkSrcClkReq[3]" = "3" register "PcieClkSrcClkReq[3]" = "3"
#Enable I2S Audio, SSP0, SSP1 and DMIC0 #Enable I2S Audio, SSP0, SSP1 and DMIC0, default DMIC1 N/A (by variants override)
register "PchHdaDspEnable" = "1" register "PchHdaDspEnable" = "1"
register "PchHdaAudioLinkSsp0" = "1" register "PchHdaAudioLinkSsp0" = "1"
register "PchHdaAudioLinkSsp1" = "1" register "PchHdaAudioLinkSsp1" = "1"
register "PchHdaAudioLinkDmic0" = "1" register "PchHdaAudioLinkDmic0" = "1"
register "PchHdaAudioLinkDmic1" = "0"
# GPIO PM programming # GPIO PM programming
register "gpio_override_pm" = "1" register "gpio_override_pm" = "1"

3
src/mainboard/google/hatch/variants/kohaku/overridetree.cb
View File

@ -20,6 +20,9 @@ chip soc/intel/cannonlake
# No PCIe WiFi # No PCIe WiFi
register "PcieRpEnable[13]" = "0" register "PcieRpEnable[13]" = "0"
# Enable DMIC1
register "PchHdaAudioLinkDmic1" = "1"
# Intel Common SoC Config # Intel Common SoC Config
#+-------------------+---------------------------+ #+-------------------+---------------------------+
#| Field | Value | #| Field | Value |