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drivers/intel/fsp2_0: Unbind UDK2015 Kconfig from FSP2.0 driver 

Now SOC code can select the require UDK support package for any
platform going forward with FSP2.0 model.

Change-Id: Ie6d1b9133892c59210a659ef0ad4b59ebf9f1e45
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23426
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Subrata Banik 2018-01-25 11:41:04 +05:30
parent 8b9f28994a
commit 74558813c0
6 changed files with 10 additions and 4 deletions
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4
src/drivers/intel/fsp2_0/Kconfig
View File

@ -1,7 +1,7 @@
#
# This file is part of the coreboot project.
#
# Copyright (C) 2015-2016 Intel Corp.
# Copyright (C) 2015-2018 Intel Corp.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
@ -15,7 +15,7 @@
config PLATFORM_USES_FSP2_0
bool
select UDK_2015_BINDING
default n
help
Include FSP 2.0 wrappers and functionality

3
src/mainboard/intel/galileo/Kconfig
View File

@ -1,7 +1,7 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2015-2017 Intel Corp.
## Copyright (C) 2015-2018 Intel Corp.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
@ -58,6 +58,7 @@ config FSP_VERSION_1_1
config FSP_VERSION_2_0
bool "FSP 2.0"
select PLATFORM_USES_FSP2_0
select UDK_2015_BINDING
select POSTCAR_STAGE
help
Use FSP 2.0 binary

2
src/soc/intel/apollolake/Kconfig
View File

@ -98,6 +98,8 @@ config CPU_SPECIFIC_OPTIONS
select TSC_MONOTONIC_TIMER
select HAVE_MONOTONIC_TIMER
select PLATFORM_USES_FSP2_0
select UDK_2015_BINDING if !SOC_INTEL_GLK
select UDK_2017_BINDING if SOC_INTEL_GLK
select HAVE_HARD_RESET
select INTEL_GMA_ADD_VBT_DATA_FILE if RUN_FSP_GOP
select HAVE_FSP_GOP

1
src/soc/intel/cannonlake/Kconfig
View File

@ -75,6 +75,7 @@ config CPU_SPECIFIC_OPTIONS
select TSC_CONSTANT_RATE
select TSC_MONOTONIC_TIMER
select UDELAY_TSC
select UDK_2017_BINDING
config UART_DEBUG
bool "Enable UART debug port."

3
src/soc/intel/denverton_ns/Kconfig
View File

@ -1,7 +1,7 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2014 - 2017 Intel Corporation.
## Copyright (C) 2014 - 2018 Intel Corporation.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
@ -50,6 +50,7 @@ config CPU_SPECIFIC_OPTIONS
select TSC_MONOTONIC_TIMER
select TSC_SYNC_MFENCE
select UDELAY_TSC
select UDK_2015_BINDING
config FSP_T_ADDR
hex "Intel FSP-T (temp ram init) binary location"

1
src/soc/intel/skylake/Kconfig
View File

@ -104,6 +104,7 @@ config USE_FSP2_0_DRIVER
def_bool y
depends on MAINBOARD_USES_FSP2_0
select PLATFORM_USES_FSP2_0
select UDK_2015_BINDING
select INTEL_GMA_ADD_VBT_DATA_FILE if RUN_FSP_GOP
select POSTCAR_CONSOLE
select POSTCAR_STAGE