diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c
index a0a790567e..0a17eadc53 100644
--- a/src/arch/x86/acpi_s3.c
+++ b/src/arch/x86/acpi_s3.c
@@ -30,22 +30,17 @@
 /* This is filled with acpi_is_wakeup() call early in ramstage. */
 static int acpi_slp_type = -1;
 
-#if IS_ENABLED(CONFIG_EARLY_CBMEM_INIT)
-int acpi_get_sleep_type(void)
-{
-	if (romstage_handoff_is_resume()) {
-		printk(BIOS_DEBUG, "S3 Resume.\n");
-		return ACPI_S3;
-	}
-	printk(BIOS_DEBUG, "Normal boot.\n");
-	return ACPI_S0;
-}
-#endif
-
 static void acpi_handoff_wakeup(void)
 {
-	if (acpi_slp_type < 0)
-		acpi_slp_type = acpi_get_sleep_type();
+	if (acpi_slp_type < 0) {
+		if (romstage_handoff_is_resume()) {
+			printk(BIOS_DEBUG, "S3 Resume.\n");
+			acpi_slp_type = ACPI_S3;
+		} else {
+			printk(BIOS_DEBUG, "Normal boot.\n");
+			acpi_slp_type = ACPI_S0;
+		}
+	}
 }
 
 int acpi_is_wakeup(void)
diff --git a/src/southbridge/amd/agesa/hudson/ramtop.c b/src/southbridge/amd/agesa/hudson/ramtop.c
index 34cf74ebd2..22b291d1bb 100644
--- a/src/southbridge/amd/agesa/hudson/ramtop.c
+++ b/src/southbridge/amd/agesa/hudson/ramtop.c
@@ -19,8 +19,6 @@
 #include <cbmem.h>
 #include "hudson.h"
 
-#if !ENV_RAMSTAGE || IS_ENABLED(CONFIG_LATE_CBMEM_INIT)
-
 int acpi_get_sleep_type(void)
 {
 	u16 tmp = inw(ACPI_PM1_CNT_BLK);
@@ -28,8 +26,6 @@ int acpi_get_sleep_type(void)
 	return (int)tmp;
 }
 
-#endif
-
 void backup_top_of_low_cacheable(uintptr_t ramtop)
 {
 	u32 dword = ramtop;
diff --git a/src/southbridge/amd/cimx/sb800/ramtop.c b/src/southbridge/amd/cimx/sb800/ramtop.c
index 2281f83958..3c685767bc 100644
--- a/src/southbridge/amd/cimx/sb800/ramtop.c
+++ b/src/southbridge/amd/cimx/sb800/ramtop.c
@@ -19,8 +19,6 @@
 #include <cbmem.h>
 #include "SBPLATFORM.h"
 
-#if !ENV_RAMSTAGE || IS_ENABLED(CONFIG_LATE_CBMEM_INIT)
-
 int acpi_get_sleep_type(void)
 {
 	u16 tmp = inw(PM1_CNT_BLK_ADDRESS);
@@ -28,8 +26,6 @@ int acpi_get_sleep_type(void)
 	return (int)tmp;
 }
 
-#endif
-
 void backup_top_of_low_cacheable(uintptr_t ramtop)
 {
 	u32 dword = ramtop;