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amd/stoneyridge: Define bits for AcpiConfig 

Add defintions for PMx74.

Change-Id: Id9483be9032abe6fbd5a6ec2af6bb8869a4ab766
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22426
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Marshall Dawson 2017-11-10 16:33:21 -07:00 committed by Martin Roth
parent cbdf9762d7
commit 7465b9dc8d
1 changed files with 13 additions and 0 deletions
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13
src/soc/amd/stoneyridge/include/soc/southbridge.h
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@ -73,6 +73,19 @@
#define PM_GPE0_BLK 0x68 #define PM_GPE0_BLK 0x68
#define PM_ACPI_SMI_CMD 0x6a #define PM_ACPI_SMI_CMD 0x6a
#define PM_ACPI_CONF 0x74 #define PM_ACPI_CONF 0x74
#define PM_ACPI_DECODE_STD BIT(0)
#define PM_ACPI_GLOBAL_EN BIT(1)
#define PM_ACPI_RTC_EN_EN BIT(2)
#define PM_ACPI_TIMER_EN_EN BIT(4)
#define PM_ACPI_MASK_ARB_DIS BIT(6)
#define PM_ACPI_BIOS_RLS BIT(7)
#define PM_ACPI_PWRBTNEN_EN BIT(8)
#define PM_ACPI_REDUCED_HW_EN BIT(9)
#define PM_ACPI_BLOCK_PCIE_PME BIT(24)
#define PM_ACPI_PCIE_WAK_MASK BIT(25)
#define PM_ACPI_WAKE_AS_GEVENT BIT(27)
#define PM_ACPI_NB_PME_GEVENT BIT(28)
#define PM_ACPI_RTC_WAKE_EN BIT(29)
#define PM_RST_CTRL1 0xbe #define PM_RST_CTRL1 0xbe
#define SLPTYPE_CONTROL_EN BIT(5) #define SLPTYPE_CONTROL_EN BIT(5)
#define PM_PMIO_DEBUG 0xd2 #define PM_PMIO_DEBUG 0xd2