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mainboard/ocp/wedge100s: Add vboot support 

* Add RO only FMAP.
* Add kconfig options.

Tested=OCP Wedge100s

Change-Id: I1979e0263e41f21c01c407ac81ad1198a53741e8
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/29593
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Philipp Deppenwiese 2018-11-12 12:15:15 +01:00
parent c14ad8a84d
commit 7470c902d8
3 changed files with 33 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
src/mainboard/ocp/wedge100s/Kconfig
View File

@ -16,6 +16,14 @@ config BOARD_SPECIFIC_OPTIONS
select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_LPC_TPM
select MAINBOARD_HAS_TPM1 select MAINBOARD_HAS_TPM1
config VBOOT
select VBOOT_VBNV_CMOS
select VBOOT_NO_BOARD_SUPPORT
select GBB_FLAG_DISABLE_LID_SHUTDOWN
select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC
select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
select GBB_FLAG_DISABLE_FWMP
config MAINBOARD_DIR config MAINBOARD_DIR
string string
default "ocp/wedge100s" default "ocp/wedge100s"
@ -30,6 +38,7 @@ config IRQ_SLOT_COUNT
config CBFS_SIZE config CBFS_SIZE
hex hex
default 0x006fa000 if VBOOT
default 0x00200000 default 0x00200000
config VIRTUAL_ROM_SIZE config VIRTUAL_ROM_SIZE
@ -45,6 +54,7 @@ config FSP_PACKAGE_DEFAULT
config FMDFILE config FMDFILE
string string
default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-ro.fmd" if VBOOT
default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd" default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd"
endif # BOARD_OCP_WEDGE100S endif # BOARD_OCP_WEDGE100S

1
src/mainboard/ocp/wedge100s/cmos.layout
View File

@ -81,6 +81,7 @@ entries
408 1 e 1 nmi 408 1 e 1 nmi
409 2 e 7 power_on_after_fail 409 2 e 7 power_on_after_fail
#411 5 r 0 unused #411 5 r 0 unused
416 128 r 0 vbnv
# MRC Scrambler Seed values # MRC Scrambler Seed values
896 32 r 0 mrc_scrambler_seed 896 32 r 0 mrc_scrambler_seed

22
src/mainboard/ocp/wedge100s/vboot-ro.fmd Normal file
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@ -0,0 +1,22 @@
FLASH 16M {
SI_ALL@0x0 0x800000 {
SI_DESC@0x0 0x1000
SI_ME@0x1000 0x7ff000
}
SI_BIOS@0x800000 0x800000 {
MISC_RW@0x0 0x20000 {
RW_MRC_CACHE@0x0 0x10000
RW_VPD@0x010000 0x4000
}
WP_RO@0x020000 0x7e0000 {
RO_VPD@0x0 0x4000
RO_SECTION@0x4000 0x7dc000 {
FMAP@0x0 0x800
RO_FRID@0x800 0x40
RO_FRID_PAD@0x840 0x7c0
GBB@0x1000 0xef000
COREBOOT(CBFS)@0xf0000 0x6ec000
}
}
}
}